git: 7b80c8b7d8d9 - main - cxgbe(4): Expanded interrupt handling for T7
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Date: Thu, 13 Nov 2025 19:27:42 UTC
The branch main has been updated by np:
URL: https://cgit.FreeBSD.org/src/commit/?id=7b80c8b7d8d9a4a634c5fd5334a9fe40f9ca0b3b
commit 7b80c8b7d8d9a4a634c5fd5334a9fe40f9ca0b3b
Author: Navdeep Parhar <np@FreeBSD.org>
AuthorDate: 2025-11-12 01:27:40 +0000
Commit: Navdeep Parhar <np@FreeBSD.org>
CommitDate: 2025-11-13 19:11:58 +0000
cxgbe(4): Expanded interrupt handling for T7
- Catch up with the new cause/perr registers. The high level approach
is the same but the T7 has an extra top level INT_CAUSE concentrator
and a PERR_CAUSE concentrator with a changed layout.
- Add various flags to control the interrupt handlers' behavior.
- Implement a t4_intr_clear that internally use the slow handler as an
iterator over known cause/perr registers. This lets the driver clear
all of the interrupt sources that it knows about. The firmware sets
up the interrupt enables and clears the causes normally so this call
should be redundant.
MFC after: 1 week
Sponsored by: Chelsio Communications
---
sys/dev/cxgbe/adapter.h | 12 +-
sys/dev/cxgbe/common/common.h | 3 +-
sys/dev/cxgbe/common/t4_hw.c | 1486 +++++++++++++++++++++++++++++++++--------
sys/dev/cxgbe/t4_main.c | 9 +-
sys/dev/cxgbe/t4_sge.c | 3 +-
5 files changed, 1214 insertions(+), 299 deletions(-)
diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h
index 0946c3110817..38875b535067 100644
--- a/sys/dev/cxgbe/adapter.h
+++ b/sys/dev/cxgbe/adapter.h
@@ -184,7 +184,16 @@ enum {
DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
- DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
+
+ /* adapter intr handler flags */
+ IHF_INTR_CLEAR_ON_INIT = (1 << 0), /* Driver calls t4_intr_clear */
+ IHF_NO_SHOW = (1 << 1), /* Do not display intr info */
+ IHF_VERBOSE = (1 << 2), /* Display extra intr info */
+ IHF_FATAL_IFF_ENABLED = (1 << 3), /* Fatal only if enabled */
+ IHF_IGNORE_IF_DISABLED = (1 << 4), /* Ignore if disabled */
+ IHF_CLR_ALL_SET = (1 << 5), /* Clear all set bits */
+ IHF_CLR_ALL_UNIGNORED = (1 << 6), /* Clear all unignored bits */
+ IHF_RUN_ALL_ACTIONS = (1 << 7), /* As if all cause are set */
};
#define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING)
@@ -1027,6 +1036,7 @@ struct adapter {
int flags;
int debug_flags;
int error_flags; /* Used by error handler and live reset. */
+ int intr_flags; /* Used by interrupt setup/handlers. */
char ifp_lockname[16];
struct mtx ifp_lock;
diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index 6b36832a7464..2033967ffb94 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -684,9 +684,10 @@ u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
struct fw_filter_wr;
+void t4_intr_clear(struct adapter *adapter);
void t4_intr_enable(struct adapter *adapter);
void t4_intr_disable(struct adapter *adapter);
-bool t4_slow_intr_handler(struct adapter *adapter, bool verbose);
+bool t4_slow_intr_handler(struct adapter *adapter, int flags);
int t4_hash_mac_addr(const u8 *addr);
int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 1fd1c36c1f25..0f25c73b99d4 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -570,11 +570,11 @@ static int t4_edc_err_read(struct adapter *adap, int idx)
edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
CH_WARN(adap,
- "edc%d err addr 0x%x: 0x%x.\n",
+ " edc%d err addr 0x%x: 0x%x.\n",
idx, edc_ecc_err_addr_reg,
t4_read_reg(adap, edc_ecc_err_addr_reg));
CH_WARN(adap,
- "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
+ " bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
edc_bist_status_rdata_reg,
(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
@@ -4777,10 +4777,9 @@ struct intr_details {
struct intr_action {
u32 mask;
int arg;
- bool (*action)(struct adapter *, int, bool);
+ bool (*action)(struct adapter *, int, int);
};
-#define NONFATAL_IF_DISABLED 1
struct intr_info {
const char *name; /* name of the INT_CAUSE register */
int cause_reg; /* INT_CAUSE register */
@@ -4803,73 +4802,78 @@ intr_alert_char(u32 cause, u32 enable, u32 fatal)
}
static void
-t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
+show_intr_info(struct adapter *sc, const struct intr_info *ii, uint32_t cause,
+ uint32_t ucause, uint32_t enabled, uint32_t fatal, int flags)
{
- u32 enable, fatal, leftover;
+ uint32_t leftover, msgbits;
const struct intr_details *details;
char alert;
+ const bool verbose = flags & IHF_VERBOSE;
- enable = t4_read_reg(adap, ii->enable_reg);
- if (ii->flags & NONFATAL_IF_DISABLED)
- fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
- else
- fatal = ii->fatal;
- alert = intr_alert_char(cause, enable, fatal);
- CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
- alert, ii->name, ii->cause_reg, cause, enable, fatal);
+ if (verbose || ucause != 0 || flags & IHF_RUN_ALL_ACTIONS) {
+ alert = intr_alert_char(cause, enabled, fatal);
+ CH_ALERT(sc, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", alert,
+ ii->name, ii->cause_reg, cause, enabled, fatal);
+ }
- leftover = cause;
+ leftover = verbose ? cause : ucause;
for (details = ii->details; details && details->mask != 0; details++) {
- u32 msgbits = details->mask & cause;
+ msgbits = details->mask & leftover;
if (msgbits == 0)
continue;
- alert = intr_alert_char(msgbits, enable, ii->fatal);
- CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits,
- details->msg);
+ alert = intr_alert_char(msgbits, enabled, fatal);
+ CH_ALERT(sc, " %c [0x%08x] %s\n", alert, msgbits, details->msg);
leftover &= ~msgbits;
}
- if (leftover != 0 && leftover != cause)
- CH_ALERT(adap, " ? [0x%08x]\n", leftover);
+ if (leftover != 0 && leftover != (verbose ? cause : ucause))
+ CH_ALERT(sc, " ? [0x%08x]\n", leftover);
}
/*
* Returns true for fatal error.
*/
static bool
-t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
- u32 additional_cause, bool verbose)
+t4_handle_intr(struct adapter *sc, const struct intr_info *ii, uint32_t acause,
+ int flags)
{
- u32 cause, fatal;
+ uint32_t cause, ucause, enabled, fatal;
bool rc;
const struct intr_action *action;
- /*
- * Read and display cause. Note that the top level PL_INT_CAUSE is a
- * bit special and we need to completely ignore the bits that are not in
- * PL_INT_ENABLE.
- */
- cause = t4_read_reg(adap, ii->cause_reg);
- if (ii->cause_reg == A_PL_INT_CAUSE)
- cause &= t4_read_reg(adap, ii->enable_reg);
- if (verbose || cause != 0)
- t4_show_intr_info(adap, ii, cause);
- fatal = cause & ii->fatal;
- if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
- fatal &= t4_read_reg(adap, ii->enable_reg);
- cause |= additional_cause;
- if (cause == 0)
- return (false);
+ cause = t4_read_reg(sc, ii->cause_reg);
+ enabled = t4_read_reg(sc, ii->enable_reg);
+ flags |= ii->flags;
+ fatal = ii->fatal & cause;
+ if (flags & IHF_FATAL_IFF_ENABLED)
+ fatal &= enabled;
+ ucause = cause;
+ if (flags & IHF_IGNORE_IF_DISABLED)
+ ucause &= enabled;
+ if (!(flags & IHF_NO_SHOW))
+ show_intr_info(sc, ii, cause, ucause, enabled, fatal, flags);
rc = fatal != 0;
for (action = ii->actions; action && action->mask != 0; action++) {
- if (!(action->mask & cause))
+ if (action->action == NULL)
continue;
- rc |= (action->action)(adap, action->arg, verbose);
+ if (action->mask & (ucause | acause) ||
+ flags & IHF_RUN_ALL_ACTIONS) {
+ bool rc1 = (action->action)(sc, action->arg, flags);
+ if (action->mask & ucause)
+ rc |= rc1;
+ }
}
/* clear */
- t4_write_reg(adap, ii->cause_reg, cause);
- (void)t4_read_reg(adap, ii->cause_reg);
+ if (cause != 0) {
+ if (flags & IHF_CLR_ALL_SET) {
+ t4_write_reg(sc, ii->cause_reg, cause);
+ (void)t4_read_reg(sc, ii->cause_reg);
+ } else if (ucause != 0 && flags & IHF_CLR_ALL_UNIGNORED) {
+ t4_write_reg(sc, ii->cause_reg, ucause);
+ (void)t4_read_reg(sc, ii->cause_reg);
+ }
+ }
return (rc);
}
@@ -4877,7 +4881,7 @@ t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
/*
* Interrupt handler for the PCIE module.
*/
-static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool pcie_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details sysbus_intr_details[] = {
{ F_RNPP, "RXNP array parity error" },
@@ -4990,21 +4994,43 @@ static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_PCIE_INT_CAUSE,
.enable_reg = A_PCIE_INT_ENABLE,
.fatal = 0xffffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ struct intr_info pcie_int_cause_ext = {
+ .name = "PCIE_INT_CAUSE_EXT",
+ .cause_reg = A_PCIE_INT_CAUSE_EXT,
+ .enable_reg = A_PCIE_INT_ENABLE_EXT,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ struct intr_info pcie_int_cause_x8 = {
+ .name = "PCIE_INT_CAUSE_X8",
+ .cause_reg = A_PCIE_INT_CAUSE_X8,
+ .enable_reg = A_PCIE_INT_ENABLE_X8,
+ .fatal = 0,
+ .flags = 0,
.details = NULL,
.actions = NULL,
};
bool fatal = false;
if (is_t4(adap)) {
- fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, flags);
pcie_intr_info.details = pcie_intr_details;
} else {
pcie_intr_info.details = t5_pcie_intr_details;
}
- fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, flags);
+ if (chip_id(adap) > CHELSIO_T6) {
+ fatal |= t4_handle_intr(adap, &pcie_int_cause_ext, 0, flags);
+ fatal |= t4_handle_intr(adap, &pcie_int_cause_x8, 0, flags);
+ }
return (fatal);
}
@@ -5012,7 +5038,7 @@ static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
/*
* TP interrupt handler.
*/
-static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool tp_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details tp_intr_details[] = {
{ 0x3fffffff, "TP parity error" },
@@ -5024,25 +5050,90 @@ static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_TP_INT_CAUSE,
.enable_reg = A_TP_INT_ENABLE,
.fatal = 0x7fffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = tp_intr_details,
.actions = NULL,
};
+ static const struct intr_info tp_inic_perr_cause = {
+ .name = "TP_INIC_PERR_CAUSE",
+ .cause_reg = A_TP_INIC_PERR_CAUSE,
+ .enable_reg = A_TP_INIC_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info tp_c_perr_cause = {
+ .name = "TP_C_PERR_CAUSE",
+ .cause_reg = A_TP_C_PERR_CAUSE,
+ .enable_reg = A_TP_C_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info tp_e_eg_perr_cause = {
+ .name = "TP_E_EG_PERR_CAUSE",
+ .cause_reg = A_TP_E_EG_PERR_CAUSE,
+ .enable_reg = A_TP_E_EG_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info tp_e_in0_perr_cause = {
+ .name = "TP_E_IN0_PERR_CAUSE",
+ .cause_reg = A_TP_E_IN0_PERR_CAUSE,
+ .enable_reg = A_TP_E_IN0_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info tp_e_in1_perr_cause = {
+ .name = "TP_E_IN1_PERR_CAUSE",
+ .cause_reg = A_TP_E_IN1_PERR_CAUSE,
+ .enable_reg = A_TP_E_IN1_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info tp_o_perr_cause = {
+ .name = "TP_O_PERR_CAUSE",
+ .cause_reg = A_TP_O_PERR_CAUSE,
+ .enable_reg = A_TP_O_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ bool fatal;
- return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
+ fatal = t4_handle_intr(adap, &tp_intr_info, 0, flags);
+ if (chip_id(adap) > CHELSIO_T6) {
+ fatal |= t4_handle_intr(adap, &tp_inic_perr_cause, 0, flags);
+ fatal |= t4_handle_intr(adap, &tp_c_perr_cause, 0, flags);
+ fatal |= t4_handle_intr(adap, &tp_e_eg_perr_cause, 0, flags);
+ fatal |= t4_handle_intr(adap, &tp_e_in0_perr_cause, 0, flags);
+ fatal |= t4_handle_intr(adap, &tp_e_in1_perr_cause, 0, flags);
+ fatal |= t4_handle_intr(adap, &tp_o_perr_cause, 0, flags);
+ }
+
+ return (fatal);
}
/*
* SGE interrupt handler.
*/
-static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool sge_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_info sge_int1_info = {
.name = "SGE_INT_CAUSE1",
.cause_reg = A_SGE_INT_CAUSE1,
.enable_reg = A_SGE_INT_ENABLE1,
.fatal = 0xffffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = NULL,
.actions = NULL,
};
@@ -5051,7 +5142,7 @@ static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_SGE_INT_CAUSE2,
.enable_reg = A_SGE_INT_ENABLE2,
.fatal = 0xffffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = NULL,
.actions = NULL,
};
@@ -5149,7 +5240,7 @@ static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_SGE_INT_CAUSE5,
.enable_reg = A_SGE_INT_ENABLE5,
.fatal = 0xffffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = NULL,
.actions = NULL,
};
@@ -5162,7 +5253,24 @@ static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
.details = NULL,
.actions = NULL,
};
-
+ static const struct intr_info sge_int7_info = {
+ .name = "SGE_INT_CAUSE7",
+ .cause_reg = A_SGE_INT_CAUSE7,
+ .enable_reg = A_SGE_INT_ENABLE7,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info sge_int8_info = {
+ .name = "SGE_INT_CAUSE8",
+ .cause_reg = A_SGE_INT_CAUSE8,
+ .enable_reg = A_SGE_INT_ENABLE8,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
bool fatal;
u32 v;
@@ -5173,14 +5281,18 @@ static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
}
fatal = false;
- fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int1_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &sge_int2_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &sge_int3_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &sge_int4_info, 0, flags);
if (chip_id(adap) >= CHELSIO_T5)
- fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int5_info, 0, flags);
if (chip_id(adap) >= CHELSIO_T6)
- fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &sge_int6_info, 0, flags);
+ if (chip_id(adap) >= CHELSIO_T7) {
+ fatal |= t4_handle_intr(adap, &sge_int7_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &sge_int8_info, 0, flags);
+ }
v = t4_read_reg(adap, A_SGE_ERROR_STATS);
if (v & F_ERROR_QID_VALID) {
@@ -5197,7 +5309,7 @@ static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
/*
* CIM interrupt handler.
*/
-static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool cim_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details cim_host_intr_details[] = {
/* T6+ */
@@ -5242,7 +5354,7 @@ static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_CIM_HOST_INT_CAUSE,
.enable_reg = A_CIM_HOST_INT_ENABLE,
.fatal = 0x007fffe6,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = cim_host_intr_details,
.actions = NULL,
};
@@ -5293,7 +5405,7 @@ static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
.enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
.fatal = 0x3fffeeff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = cim_host_upacc_intr_details,
.actions = NULL,
};
@@ -5306,6 +5418,15 @@ static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
.details = NULL,
.actions = NULL,
};
+ static const struct intr_info cim_perr_cause = {
+ .name = "CIM_PERR_CAUSE",
+ .cause_reg = A_CIM_PERR_CAUSE,
+ .enable_reg = A_CIM_PERR_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
u32 val, fw_err;
bool fatal;
@@ -5324,9 +5445,11 @@ static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
}
fatal = (fw_err & F_PCIE_FW_ERR) != 0;
- fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, flags);
+ fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, flags);
+ if (chip_id(adap) > CHELSIO_T6)
+ fatal |= t4_handle_intr(adap, &cim_perr_cause, 0, flags);
if (fatal)
t4_os_cim_err(adap);
@@ -5336,7 +5459,7 @@ static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
/*
* ULP RX interrupt handler.
*/
-static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool ulprx_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details ulprx_intr_details[] = {
/* T5+ */
@@ -5354,7 +5477,7 @@ static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_ULP_RX_INT_CAUSE,
.enable_reg = A_ULP_RX_INT_ENABLE,
.fatal = 0x07ffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = ulprx_intr_details,
.actions = NULL,
};
@@ -5367,10 +5490,53 @@ static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
.details = NULL,
.actions = NULL,
};
+ static const struct intr_info ulprx_int_cause_pcmd = {
+ .name = "ULP_RX_INT_CAUSE_PCMD",
+ .cause_reg = A_ULP_RX_INT_CAUSE_PCMD,
+ .enable_reg = A_ULP_RX_INT_ENABLE_PCMD,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulprx_int_cause_data = {
+ .name = "ULP_RX_INT_CAUSE_DATA",
+ .cause_reg = A_ULP_RX_INT_CAUSE_DATA,
+ .enable_reg = A_ULP_RX_INT_ENABLE_DATA,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulprx_int_cause_arb = {
+ .name = "ULP_RX_INT_CAUSE_ARB",
+ .cause_reg = A_ULP_RX_INT_CAUSE_ARB,
+ .enable_reg = A_ULP_RX_INT_ENABLE_ARB,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulprx_int_cause_intf = {
+ .name = "ULP_RX_INT_CAUSE_INTERFACE",
+ .cause_reg = A_ULP_RX_INT_CAUSE_INTERFACE,
+ .enable_reg = A_ULP_RX_INT_ENABLE_INTERFACE,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
bool fatal = false;
- fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, flags);
+ if (chip_id(adap) < CHELSIO_T7)
+ fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, flags);
+ else {
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_pcmd, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_data, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_arb, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulprx_int_cause_intf, 0, flags);
+ }
return (fatal);
}
@@ -5378,7 +5544,7 @@ static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
/*
* ULP TX interrupt handler.
*/
-static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool ulptx_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details ulptx_intr_details[] = {
{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
@@ -5393,32 +5559,98 @@ static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_ULP_TX_INT_CAUSE,
.enable_reg = A_ULP_TX_INT_ENABLE,
.fatal = 0x0fffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = ulptx_intr_details,
.actions = NULL,
};
- static const struct intr_info ulptx_intr2_info = {
+ static const struct intr_info ulptx_intr_info2 = {
.name = "ULP_TX_INT_CAUSE_2",
.cause_reg = A_ULP_TX_INT_CAUSE_2,
.enable_reg = A_ULP_TX_INT_ENABLE_2,
- .fatal = 0xf0,
- .flags = NONFATAL_IF_DISABLED,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulptx_intr_info3 = {
+ .name = "ULP_TX_INT_CAUSE_3",
+ .cause_reg = A_ULP_TX_INT_CAUSE_3,
+ .enable_reg = A_ULP_TX_INT_ENABLE_3,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulptx_intr_info4 = {
+ .name = "ULP_TX_INT_CAUSE_4",
+ .cause_reg = A_ULP_TX_INT_CAUSE_4,
+ .enable_reg = A_ULP_TX_INT_ENABLE_4,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulptx_intr_info5 = {
+ .name = "ULP_TX_INT_CAUSE_5",
+ .cause_reg = A_ULP_TX_INT_CAUSE_5,
+ .enable_reg = A_ULP_TX_INT_ENABLE_5,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulptx_intr_info6 = {
+ .name = "ULP_TX_INT_CAUSE_6",
+ .cause_reg = A_ULP_TX_INT_CAUSE_6,
+ .enable_reg = A_ULP_TX_INT_ENABLE_6,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulptx_intr_info7 = {
+ .name = "ULP_TX_INT_CAUSE_7",
+ .cause_reg = A_ULP_TX_INT_CAUSE_7,
+ .enable_reg = A_ULP_TX_INT_ENABLE_7,
+ .fatal = 0,
+ .flags = 0,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info ulptx_intr_info8 = {
+ .name = "ULP_TX_INT_CAUSE_8",
+ .cause_reg = A_ULP_TX_INT_CAUSE_8,
+ .enable_reg = A_ULP_TX_INT_ENABLE_8,
+ .fatal = 0,
+ .flags = 0,
.details = NULL,
.actions = NULL,
};
bool fatal = false;
- fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
- fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, flags);
+ if (chip_id(adap) > CHELSIO_T4)
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, flags);
+ if (chip_id(adap) > CHELSIO_T6) {
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info3, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info4, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info5, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info6, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info7, 0, flags);
+ fatal |= t4_handle_intr(adap, &ulptx_intr_info8, 0, flags);
+ }
return (fatal);
}
-static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
+static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, int flags)
{
int i;
u32 data[17];
+ if (flags & IHF_NO_SHOW)
+ return (false);
+
t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
for (i = 0; i < ARRAY_SIZE(data); i++) {
@@ -5432,13 +5664,9 @@ static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
/*
* PM TX interrupt handler.
*/
-static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool pmtx_intr_handler(struct adapter *adap, int arg, int flags)
{
- static const struct intr_action pmtx_intr_actions[] = {
- { 0xffffffff, 0, pmtx_dump_dbg_stats },
- { 0 },
- };
- static const struct intr_details pmtx_intr_details[] = {
+ static const struct intr_details pmtx_int_cause_fields[] = {
{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
@@ -5455,25 +5683,29 @@ static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
{ F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
{ 0 }
};
- static const struct intr_info pmtx_intr_info = {
+ static const struct intr_action pmtx_int_cause_actions[] = {
+ { 0xffffffff, -1, pmtx_dump_dbg_stats },
+ { 0 },
+ };
+ static const struct intr_info pmtx_int_cause = {
.name = "PM_TX_INT_CAUSE",
.cause_reg = A_PM_TX_INT_CAUSE,
.enable_reg = A_PM_TX_INT_ENABLE,
.fatal = 0xffffffff,
.flags = 0,
- .details = pmtx_intr_details,
- .actions = pmtx_intr_actions,
+ .details = pmtx_int_cause_fields,
+ .actions = pmtx_int_cause_actions,
};
- return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
+ return (t4_handle_intr(adap, &pmtx_int_cause, 0, flags));
}
/*
* PM RX interrupt handler.
*/
-static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool pmrx_intr_handler(struct adapter *adap, int arg, int flags)
{
- static const struct intr_details pmrx_intr_details[] = {
+ static const struct intr_details pmrx_int_cause_fields[] = {
/* T6+ */
{ 0x18000000, "PMRX ospi overflow" },
{ F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
@@ -5495,25 +5727,25 @@ static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
{ F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
{ 0 }
};
- static const struct intr_info pmrx_intr_info = {
+ static const struct intr_info pmrx_int_cause = {
.name = "PM_RX_INT_CAUSE",
.cause_reg = A_PM_RX_INT_CAUSE,
.enable_reg = A_PM_RX_INT_ENABLE,
.fatal = 0x1fffffff,
- .flags = NONFATAL_IF_DISABLED,
- .details = pmrx_intr_details,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = pmrx_int_cause_fields,
.actions = NULL,
};
- return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
+ return (t4_handle_intr(adap, &pmrx_int_cause, 0, flags));
}
/*
* CPL switch interrupt handler.
*/
-static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool cplsw_intr_handler(struct adapter *adap, int arg, int flags)
{
- static const struct intr_details cplsw_intr_details[] = {
+ static const struct intr_details cplsw_int_cause_fields[] = {
/* T5+ */
{ F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
{ F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
@@ -5527,17 +5759,17 @@ static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
{ F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
{ 0 }
};
- static const struct intr_info cplsw_intr_info = {
+ static const struct intr_info cplsw_int_cause = {
.name = "CPL_INTR_CAUSE",
.cause_reg = A_CPL_INTR_CAUSE,
.enable_reg = A_CPL_INTR_ENABLE,
- .fatal = 0xff,
- .flags = NONFATAL_IF_DISABLED,
- .details = cplsw_intr_details,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = cplsw_int_cause_fields,
.actions = NULL,
};
- return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
+ return (t4_handle_intr(adap, &cplsw_int_cause, 0, flags));
}
#define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
@@ -5549,11 +5781,12 @@ static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
#define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
+#define T7_LE_FATAL_MASK (T6_LE_FATAL_MASK | F_CACHESRAMPERR | F_CACHEINTPERR)
/*
* LE interrupt handler.
*/
-static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool le_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details le_intr_details[] = {
{ F_REQQPARERR, "LE request queue parity error" },
@@ -5590,7 +5823,7 @@ static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_LE_DB_INT_CAUSE,
.enable_reg = A_LE_DB_INT_ENABLE,
.fatal = 0,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = NULL,
.actions = NULL,
};
@@ -5600,16 +5833,19 @@ static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
le_intr_info.fatal = T5_LE_FATAL_MASK;
} else {
le_intr_info.details = t6_le_intr_details;
- le_intr_info.fatal = T6_LE_FATAL_MASK;
+ if (chip_id(adap) < CHELSIO_T7)
+ le_intr_info.fatal = T6_LE_FATAL_MASK;
+ else
+ le_intr_info.fatal = T7_LE_FATAL_MASK;
}
- return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
+ return (t4_handle_intr(adap, &le_intr_info, 0, flags));
}
/*
* MPS interrupt handler.
*/
-static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
+static bool mps_intr_handler(struct adapter *adap, int arg, int flags)
{
static const struct intr_details mps_rx_perr_intr_details[] = {
{ 0xffffffff, "MPS Rx parity error" },
@@ -5620,10 +5856,55 @@ static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_MPS_RX_PERR_INT_CAUSE,
.enable_reg = A_MPS_RX_PERR_INT_ENABLE,
.fatal = 0xffffffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = mps_rx_perr_intr_details,
.actions = NULL,
};
+ static const struct intr_info mps_rx_perr_intr_info2 = {
+ .name = "MPS_RX_PERR_INT_CAUSE2",
+ .cause_reg = A_MPS_RX_PERR_INT_CAUSE2,
+ .enable_reg = A_MPS_RX_PERR_INT_ENABLE2,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_rx_perr_intr_info3 = {
+ .name = "MPS_RX_PERR_INT_CAUSE3",
+ .cause_reg = A_MPS_RX_PERR_INT_CAUSE3,
+ .enable_reg = A_MPS_RX_PERR_INT_ENABLE3,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_rx_perr_intr_info4 = {
+ .name = "MPS_RX_PERR_INT_CAUSE4",
+ .cause_reg = A_MPS_RX_PERR_INT_CAUSE4,
+ .enable_reg = A_MPS_RX_PERR_INT_ENABLE4,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_rx_perr_intr_info5 = {
+ .name = "MPS_RX_PERR_INT_CAUSE5",
+ .cause_reg = A_MPS_RX_PERR_INT_CAUSE5,
+ .enable_reg = A_MPS_RX_PERR_INT_ENABLE5,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_rx_perr_intr_info6 = {
+ .name = "MPS_RX_PERR_INT_CAUSE6",
+ .cause_reg = A_MPS_RX_PERR_INT_CAUSE6,
+ .enable_reg = A_MPS_RX_PERR_INT_ENABLE6,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
static const struct intr_details mps_tx_intr_details[] = {
{ F_PORTERR, "MPS Tx destination port is disabled" },
{ F_FRMERR, "MPS Tx framing error" },
@@ -5640,10 +5921,37 @@ static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_MPS_TX_INT_CAUSE,
.enable_reg = A_MPS_TX_INT_ENABLE,
.fatal = 0x1ffff,
- .flags = NONFATAL_IF_DISABLED,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = mps_tx_intr_details,
.actions = NULL,
};
+ static const struct intr_info mps_tx_intr_info2 = {
+ .name = "MPS_TX_INT2_CAUSE",
+ .cause_reg = A_MPS_TX_INT2_CAUSE,
+ .enable_reg = A_MPS_TX_INT2_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_tx_intr_info3 = {
+ .name = "MPS_TX_INT3_CAUSE",
+ .cause_reg = A_MPS_TX_INT3_CAUSE,
+ .enable_reg = A_MPS_TX_INT3_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
+ static const struct intr_info mps_tx_intr_info4 = {
+ .name = "MPS_TX_INT4_CAUSE",
+ .cause_reg = A_MPS_TX_INT4_CAUSE,
+ .enable_reg = A_MPS_TX_INT4_ENABLE,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
static const struct intr_details mps_trc_intr_details[] = {
{ F_MISCPERR, "MPS TRC misc parity error" },
{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
@@ -5660,14 +5968,23 @@ static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
.actions = NULL,
};
static const struct intr_info t7_mps_trc_intr_info = {
- .name = "T7_MPS_TRC_INT_CAUSE",
+ .name = "MPS_TRC_INT_CAUSE",
.cause_reg = A_T7_MPS_TRC_INT_CAUSE,
.enable_reg = A_T7_MPS_TRC_INT_ENABLE,
- .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
- .flags = 0,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
.details = mps_trc_intr_details,
.actions = NULL,
};
+ static const struct intr_info t7_mps_trc_intr_info2 = {
+ .name = "MPS_TRC_INT_CAUSE2",
+ .cause_reg = A_MPS_TRC_INT_CAUSE2,
+ .enable_reg = A_MPS_TRC_INT_ENABLE2,
+ .fatal = 0xffffffff,
+ .flags = IHF_FATAL_IFF_ENABLED,
+ .details = NULL,
+ .actions = NULL,
+ };
static const struct intr_details mps_stat_sram_intr_details[] = {
{ 0xffffffff, "MPS statistics SRAM parity error" },
{ 0 }
@@ -5677,7 +5994,7 @@ static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
.fatal = 0x1fffffff,
*** 1291 LINES SKIPPED ***