git: 054da4a6d033 - releng/15.0 - riscv: Treat pointer register as an input in fpe_store

The branch releng/15.0 has been updated by cperciva:

URL: https://cgit.FreeBSD.org/src/commit/?id=054da4a6d033feb1948d609a0dc20a1c82bc8943

commit 054da4a6d033feb1948d609a0dc20a1c82bc8943
Author:     John Baldwin <jhb@FreeBSD.org>
AuthorDate: 2025-10-30 19:52:51 +0000
Commit:     Colin Percival <cperciva@FreeBSD.org>
CommitDate: 2025-11-05 20:18:00 +0000

    riscv: Treat pointer register as an input in fpe_store
    
    The contents of the memory is an output, but the pointer to that memory
    is an input. This was correct in the original version of D45697, but
    when adding appropriate clobbers, the pointer operand was incorrectly
    switched to an output rather than left an input for fpe_store.
    
    Approved by:    re (cperciva)
    Reviewed by:    jrtc27
    Obtained from:  CheriBSD
    Fixes:          44d4ee7f3dad ("riscv: add FPE code.")
    MFC after:      1 day
    Sponsored by:   AFRL, DARPA
    Differential Revision:  https://reviews.freebsd.org/D53441
    
    (cherry picked from commit 91f66f9b377e09f59f481e653d8f64120a183806)
    (cherry picked from commit 0b5e4af65d0d3dfaa318b8e6adaaa4297f94af17)
---
 sys/riscv/riscv/fpe.c | 66 +++++++++++++++++++++++++--------------------------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/sys/riscv/riscv/fpe.c b/sys/riscv/riscv/fpe.c
index b6c66e5e4f09..63103a794a8e 100644
--- a/sys/riscv/riscv/fpe.c
+++ b/sys/riscv/riscv/fpe.c
@@ -69,39 +69,39 @@ fpe_store(struct fpreg *regs)
 
 	__asm __volatile(
 	    "frcsr	%0		\n"
-	    "fsd	f0, (16 * 0)(%1)\n"
-	    "fsd	f1, (16 * 1)(%1)\n"
-	    "fsd	f2, (16 * 2)(%1)\n"
-	    "fsd	f3, (16 * 3)(%1)\n"
-	    "fsd	f4, (16 * 4)(%1)\n"
-	    "fsd	f5, (16 * 5)(%1)\n"
-	    "fsd	f6, (16 * 6)(%1)\n"
-	    "fsd	f7, (16 * 7)(%1)\n"
-	    "fsd	f8, (16 * 8)(%1)\n"
-	    "fsd	f9, (16 * 9)(%1)\n"
-	    "fsd	f10, (16 * 10)(%1)\n"
-	    "fsd	f11, (16 * 11)(%1)\n"
-	    "fsd	f12, (16 * 12)(%1)\n"
-	    "fsd	f13, (16 * 13)(%1)\n"
-	    "fsd	f14, (16 * 14)(%1)\n"
-	    "fsd	f15, (16 * 15)(%1)\n"
-	    "fsd	f16, (16 * 16)(%1)\n"
-	    "fsd	f17, (16 * 17)(%1)\n"
-	    "fsd	f18, (16 * 18)(%1)\n"
-	    "fsd	f19, (16 * 19)(%1)\n"
-	    "fsd	f20, (16 * 20)(%1)\n"
-	    "fsd	f21, (16 * 21)(%1)\n"
-	    "fsd	f22, (16 * 22)(%1)\n"
-	    "fsd	f23, (16 * 23)(%1)\n"
-	    "fsd	f24, (16 * 24)(%1)\n"
-	    "fsd	f25, (16 * 25)(%1)\n"
-	    "fsd	f26, (16 * 26)(%1)\n"
-	    "fsd	f27, (16 * 27)(%1)\n"
-	    "fsd	f28, (16 * 28)(%1)\n"
-	    "fsd	f29, (16 * 29)(%1)\n"
-	    "fsd	f30, (16 * 30)(%1)\n"
-	    "fsd	f31, (16 * 31)(%1)\n"
-	    : "=&r"(fcsr), "=r"(fp_x), "=m"(*fp_x));
+	    "fsd	f0, (16 * 0)(%2)\n"
+	    "fsd	f1, (16 * 1)(%2)\n"
+	    "fsd	f2, (16 * 2)(%2)\n"
+	    "fsd	f3, (16 * 3)(%2)\n"
+	    "fsd	f4, (16 * 4)(%2)\n"
+	    "fsd	f5, (16 * 5)(%2)\n"
+	    "fsd	f6, (16 * 6)(%2)\n"
+	    "fsd	f7, (16 * 7)(%2)\n"
+	    "fsd	f8, (16 * 8)(%2)\n"
+	    "fsd	f9, (16 * 9)(%2)\n"
+	    "fsd	f10, (16 * 10)(%2)\n"
+	    "fsd	f11, (16 * 11)(%2)\n"
+	    "fsd	f12, (16 * 12)(%2)\n"
+	    "fsd	f13, (16 * 13)(%2)\n"
+	    "fsd	f14, (16 * 14)(%2)\n"
+	    "fsd	f15, (16 * 15)(%2)\n"
+	    "fsd	f16, (16 * 16)(%2)\n"
+	    "fsd	f17, (16 * 17)(%2)\n"
+	    "fsd	f18, (16 * 18)(%2)\n"
+	    "fsd	f19, (16 * 19)(%2)\n"
+	    "fsd	f20, (16 * 20)(%2)\n"
+	    "fsd	f21, (16 * 21)(%2)\n"
+	    "fsd	f22, (16 * 22)(%2)\n"
+	    "fsd	f23, (16 * 23)(%2)\n"
+	    "fsd	f24, (16 * 24)(%2)\n"
+	    "fsd	f25, (16 * 25)(%2)\n"
+	    "fsd	f26, (16 * 26)(%2)\n"
+	    "fsd	f27, (16 * 27)(%2)\n"
+	    "fsd	f28, (16 * 28)(%2)\n"
+	    "fsd	f29, (16 * 29)(%2)\n"
+	    "fsd	f30, (16 * 30)(%2)\n"
+	    "fsd	f31, (16 * 31)(%2)\n"
+	    : "=&r"(fcsr), "=m"(*fp_x) : "r"(fp_x));
 
 	regs->fp_fcsr = fcsr;
 }