From nobody Tue Mar 18 17:00:47 2025 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4ZHJ4x3w7Bz5qwc7; Tue, 18 Mar 2025 17:00:49 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R10" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4ZHJ4w1hfLz49tm; Tue, 18 Mar 2025 17:00:48 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1742317248; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=UWZc/I7GmaN+DSrGNgC/tSI0GossDGUwJ5JsV/YJyZ8=; b=Ze3U6p+Np0glNMbWXPa9j4dz23E+iCHudOp7l9OS1ZhAQaSXZhPiw7CFMModr3P4wSKlsF D41ohlWok3iYFja4J4ZFNzQh0636JPk9V70zt/osXY38dY7tMrq1IoeGvAwZP9fXAP30ut MNEa/0YDvvhIgaQHLYttcXtnQiC7Hib9dc5jtWxLy4nV5WM6sGk9dZah5/l6g0lp2dPhmi T0gUOYruXjkDExikQxlCzzDDj0SlLygyjI0r+wXH/BqK1d/3DtYKzNRd1rnvM8rOSpRC6K 3NzDoqZZc7U0rxvZepIywBMUV/BL4uhi1sI67HcPAR65NHS47uPYc4dnAhY1MQ== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1742317248; a=rsa-sha256; cv=none; b=wDKsWREWR3TdeYbyeBZYdn5C8BUyfWc3l4u/0jwf4/0gHQdt0HI03oNZtvGn33MbEzpwLS exZo7cy6LOc0z0r5wWU5CV15brq069x8c2qzoDysOmMr8JjXqZneAcPn5qqQjUX324QkMd ADtbcTSRKQBPBCBC4BGIqY51ADIlSDhJpuOidPZfri65YEJ/jOJfb1tHC0a25w04QSQz83 amUiZZ4FPRLyP7a0OGZ4PtlCOi52kyLhghD1MIbmG4hb/rpJzIYbM7Zd34E+qfUbR8akhD h+9OTx8rqq1LbYQwwmB6nqVxh7sjYLcbmDTISy8aEwkwik/3eSAq9w60Gklc5g== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1742317248; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=UWZc/I7GmaN+DSrGNgC/tSI0GossDGUwJ5JsV/YJyZ8=; b=nqFI2mGWgOyJr/ekqF0et4vOMtmzHwniToJ12f7THLHvZsI3qIGJZf6rRvJO50vCdyoIeM 0q6yNAknRI6PPVRTwn+e0IRu/2TnynskFN53Ob0lG+/a8mx++TSKo2Nj2Zy/cLoPF3KVae 8d4tOkPYElm4i4bVMwin7FyArzmQiWrhvyt6wGn3KQ8Mq/t/S5H9nXdq9v+X9ao+kBZsKr eoC4LW8bWjDQaxlIfXZ2btH4jlAUQ8v84bFxNNgs8Sg4I9qxlfbrh1c8XN50FJFC+rLbxk 5Ln2QtFo5geSGOV7W8gyza4bgeQkyj5ZFpB5ktVGmawIXUTtlBpJat3RoOPWrg== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4ZHJ4w0XlQzhqY; Tue, 18 Mar 2025 17:00:48 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 52IH0lhO036257; Tue, 18 Mar 2025 17:00:47 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 52IH0ltn036254; Tue, 18 Mar 2025 17:00:47 GMT (envelope-from git) Date: Tue, 18 Mar 2025 17:00:47 GMT Message-Id: <202503181700.52IH0ltn036254@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Stephen Hurd Subject: git: 0832a409c21b - main - Add driver for the RK3328 GPIO_MUTE pin List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: shurd X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 0832a409c21b45b2a31b90c50a005d9a4b1a5efd Auto-Submitted: auto-generated The branch main has been updated by shurd: URL: https://cgit.FreeBSD.org/src/commit/?id=0832a409c21b45b2a31b90c50a005d9a4b1a5efd commit 0832a409c21b45b2a31b90c50a005d9a4b1a5efd Author: Stephen Hurd AuthorDate: 2025-03-15 19:43:55 +0000 Commit: Stephen Hurd CommitDate: 2025-03-18 17:00:19 +0000 Add driver for the RK3328 GPIO_MUTE pin This is used in in the ROC-RK3328-CC to control a regulator. Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D49399 --- share/man/man4/man4.aarch64/Makefile | 1 + share/man/man4/man4.aarch64/rk_grf_gpio.4 | 44 ++++++ sys/arm/rockchip/files.rk32xx | 1 + sys/arm64/rockchip/rk_grf_gpio.c | 236 ++++++++++++++++++++++++++++++ sys/conf/files.arm64 | 1 + 5 files changed, 283 insertions(+) diff --git a/share/man/man4/man4.aarch64/Makefile b/share/man/man4/man4.aarch64/Makefile index aca11eeb583f..0e85aab8b770 100644 --- a/share/man/man4/man4.aarch64/Makefile +++ b/share/man/man4/man4.aarch64/Makefile @@ -6,6 +6,7 @@ MAN= \ felix.4 \ rk_gpio.4 \ rk_grf.4 \ + rk_grf_gpio.4 \ rk_i2c.4 \ rk_pinctrl.4 \ diff --git a/share/man/man4/man4.aarch64/rk_grf_gpio.4 b/share/man/man4/man4.aarch64/rk_grf_gpio.4 new file mode 100644 index 000000000000..1587e708c93b --- /dev/null +++ b/share/man/man4/man4.aarch64/rk_grf_gpio.4 @@ -0,0 +1,44 @@ +.\" +.\" SPDX-License-Identifier: BSD-2-Clause +.\" +.\" Copyright (c) 2025 Stephen Hurd +.\" +.Dd Mar 16, 2025 +.Dt RK_GRF_GPIO 4 +.Os +.Sh NAME +.Nm rk_grf_gpio +.Nd +.Xr gpio 3 +driver for RockChip GPIO_MUTE pin +.Sh SYNOPSIS +.Cd "options SOC_ROCKCHIP_rk3328" +.Sh DESCRIPTION +The +.Nm +driver provides a single-pin, output-only +.Xr gpio 3 +unit whose single pin is named GPIO_MUTE. This controls the output +of the GPIO_MUTE pin on the SoC. +.Pp +This gpio is usually used to control another device on the board, +so is not usually available for user software. +.Sh HARDWARE +The +.Nm +driver supports the following GRF GPIO controller: +.Pp +.Bl -bullet -compact +.It +rockchip,rk3328-grf-gpio +.El +.Sh HISTORY +The +.Nm +driver first appeared in +.Fx 15.0 . +.Sh AUTHORS +The +.Nm +driver and manual were written by +.An Stephen Hurd Aq Mt shurd@freebsd.org . diff --git a/sys/arm/rockchip/files.rk32xx b/sys/arm/rockchip/files.rk32xx index 7331b12a06ed..2faee11b0b6a 100644 --- a/sys/arm/rockchip/files.rk32xx +++ b/sys/arm/rockchip/files.rk32xx @@ -6,6 +6,7 @@ dev/iicbus/controller/rockchip/rk_i2c.c standard arm64/rockchip/rk_iodomain.c standard arm64/rockchip/rk_gpio.c standard arm64/rockchip/rk_grf.c standard +arm64/rockchip/rk_grf_gpio.c standard arm64/rockchip/rk_pinctrl.c standard arm64/rockchip/rk_pmu.c standard dev/pwm/controller/rockchip/rk_pwm.c standard diff --git a/sys/arm64/rockchip/rk_grf_gpio.c b/sys/arm64/rockchip/rk_grf_gpio.c new file mode 100644 index 000000000000..6818bd85bb95 --- /dev/null +++ b/sys/arm64/rockchip/rk_grf_gpio.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2025 Stephen Hurd + * + * SPDX-License-Identifier: BSD-2-Clause + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "syscon_if.h" + +#define GRF_SOC_CON10 0x0428 +#define SOC_CON10_GPIOMUT (1 << 1) +#define SOC_CON10_GPIOMUT_MASK ((1 << 1) << 16) +#define SOC_CON10_GPIOMUT_EN (1 << 0) +#define SOC_CON10_GPIOMUT_EN_MASK ((1 << 0) << 16) + +struct rk_grf_gpio_softc { + device_t sc_dev; + device_t sc_busdev; + struct syscon *sc_grf; + bool active_high; +}; + +static struct ofw_compat_data compat_data[] = { + {"rockchip,rk3328-grf-gpio", 1}, + {NULL, 0} +}; + +static device_t +rk_grf_gpio_get_bus(device_t dev) +{ + struct rk_grf_gpio_softc *sc; + + sc = device_get_softc(dev); + + return (sc->sc_busdev); +} + +static int +rk_grf_gpio_pin_max(device_t dev, int *maxpin) +{ + *maxpin = 1; + return (0); +} + +static int +rk_grf_gpio_pin_getname(device_t dev, uint32_t pin, char *name) +{ + if (pin) + return (EINVAL); + + snprintf(name, GPIOMAXNAME, "GPIO_MUTE"); + + return (0); +} + +static int +rk_grf_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) +{ + if (pin) + return (EINVAL); + *flags = GPIO_PIN_OUTPUT; + return (0); +} + +static int +rk_grf_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) +{ + if (pin) + return (EINVAL); + if (flags != GPIO_PIN_OUTPUT) + return (EINVAL); + + return (0); +} + +static int +rk_grf_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) +{ + if (pin) + return (EINVAL); + + *caps = GPIO_PIN_OUTPUT; + return (0); +} + +static int +rk_grf_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) +{ + struct rk_grf_gpio_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + + if (pin) + return (EINVAL); + + reg = SYSCON_READ_4(sc->sc_grf, GRF_SOC_CON10); + if (reg & SOC_CON10_GPIOMUT) + *val = 1; + else + *val = 0; + + return (0); +} + +static int +rk_grf_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) +{ + struct rk_grf_gpio_softc *sc; + uint32_t val; + + sc = device_get_softc(dev); + + if (pin) + return (EINVAL); + + val = SOC_CON10_GPIOMUT_MASK; + if (value) + val |= SOC_CON10_GPIOMUT; + SYSCON_WRITE_4(sc->sc_grf, GRF_SOC_CON10, val); + + return (0); +} + +static int +rk_grf_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, + pcell_t *gpios, uint32_t *pin, uint32_t *flags) +{ + if (gpios[0]) + return (EINVAL); + + /* The gpios are mapped as */ + *pin = 0; + /* TODO: The only valid flags are active low or active high */ + *flags = GPIO_PIN_OUTPUT; + return (0); +} + +static int +rk_grf_gpio_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "RockChip General Register File GPIO (GPIO_MUTE)"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_grf_gpio_attach(device_t dev) +{ + struct rk_grf_gpio_softc *sc; + phandle_t parent_node, node; + device_t pdev; + + sc = device_get_softc(dev); + sc->sc_dev = dev; + + node = ofw_bus_get_node(sc->sc_dev); + if (!OF_hasprop(node, "gpio-controller")) + return (ENXIO); + pdev = device_get_parent(dev); + parent_node = ofw_bus_get_node(pdev); + if (syscon_get_by_ofw_node(dev, parent_node, &sc->sc_grf) != 0) { + device_printf(dev, "cannot get parent syscon handle\n"); + return (ENXIO); + } + + sc->sc_busdev = gpiobus_attach_bus(dev); + if (sc->sc_busdev == NULL) { + return (ENXIO); + } + + return (0); +} + +static int +rk_grf_gpio_detach(device_t dev) +{ + struct rk_grf_gpio_softc *sc; + + sc = device_get_softc(dev); + + if (sc->sc_busdev) + gpiobus_detach_bus(dev); + + return(0); +} + +static device_method_t rk_grf_gpio_methods[] = { + DEVMETHOD(device_probe, rk_grf_gpio_probe), + DEVMETHOD(device_attach, rk_grf_gpio_attach), + DEVMETHOD(device_detach, rk_grf_gpio_detach), + + /* GPIO protocol */ + DEVMETHOD(gpio_get_bus, rk_grf_gpio_get_bus), + DEVMETHOD(gpio_pin_max, rk_grf_gpio_pin_max), + DEVMETHOD(gpio_pin_getname, rk_grf_gpio_pin_getname), + DEVMETHOD(gpio_pin_getflags, rk_grf_gpio_pin_getflags), + DEVMETHOD(gpio_pin_setflags, rk_grf_gpio_pin_setflags), + DEVMETHOD(gpio_pin_getcaps, rk_grf_gpio_pin_getcaps), + DEVMETHOD(gpio_pin_get, rk_grf_gpio_pin_get), + DEVMETHOD(gpio_pin_set, rk_grf_gpio_pin_set), + DEVMETHOD(gpio_map_gpios, rk_grf_gpio_map_gpios), + + DEVMETHOD_END +}; + +static driver_t rk_grf_gpio_driver = { + "gpio", + rk_grf_gpio_methods, + sizeof(struct rk_grf_gpio_softc), +}; + +/* + * GPIO driver is always a child of rk_grf driver and should be probed + * and attached within rk_grf function. Due to this, bus pass order + * must be same as bus pass order of rk_grf driver. + */ +EARLY_DRIVER_MODULE(rk_grf_gpio, simplebus, rk_grf_gpio_driver, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index de3134ad9124..480f1ac78905 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -735,6 +735,7 @@ dev/iicbus/pmic/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 dev/iicbus/pmic/rockchip/rk808.c optional fdt rk808 soc_rockchip_rk3399 dev/iicbus/pmic/rockchip/rk817.c optional fdt rk817 soc_rockchip_rk3568 arm64/rockchip/rk_grf.c optional fdt soc_rockchip +arm64/rockchip/rk_grf_gpio.c optional fdt soc_rockchip arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain