git: 4d1acfb132a5 - main - arm64: add HCRX_EL2 register

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=4d1acfb132a5e6f31fc7786ea22c3239c2573b8c

commit 4d1acfb132a5e6f31fc7786ea22c3239c2573b8c
Author:     Harry Moulton <harry.moulton@arm.com>
AuthorDate: 2025-01-23 12:28:28 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2025-01-23 17:26:26 +0000

    arm64: add HCRX_EL2 register
    
    HCRX_EL2 is the Extended Hypervisor Configuration Register introduced
    with FEAT_HCX in ARMv8.7. All fields in this register are used for
    features in ARMv8.7 and above. Initially zero the register, incase
    firmware has not properly configured it.
    
    Reviewed by:    andrew
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D48583
    Signed-off-by: Harry Moulton <harry.moulton@arm.com>
---
 sys/arm64/arm64/locore.S       | 19 ++++++++++++++++---
 sys/arm64/include/hypervisor.h | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index e721092455e8..f3b846eee412 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -351,7 +351,6 @@ LENTRY(enter_kernel_el)
 	isb
 	mrs	x4, hcr_el2
 
-
 	/* Load the Virtualization Process ID Register */
 	mrs	x2, midr_el1
 	msr	vpidr_el2, x2
@@ -400,6 +399,20 @@ LENTRY(enter_kernel_el)
 	/* Set the return PSTATE */
 	msr	spsr_el2, x5
 
+	/*
+	 * Configure the Extended Hypervisor register. This is only valid if
+	 * FEAT_HCX is enabled.
+	 */
+	mrs x2, id_aa64mmfr1_el1
+	ubfx x2, x2, #ID_AA64MMFR1_HCX_SHIFT, #ID_AA64MMFR1_HCX_WIDTH
+	cbz x2, 2f
+
+	/* Extended Hypervisor Configuration */
+	mov x2, xzr
+	msr HCRX_EL2_REG, x2
+	isb
+2:
+
 	/* Don't trap to EL2 for CP15 traps */
 	msr	hstr_el2, xzr
 
@@ -414,13 +427,13 @@ LENTRY(enter_kernel_el)
 	/* Extract GIC bits from the register */
 	ubfx	x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS
 	/* GIC[3:0] != 0000 - GIC CPU interface via special regs. supported */
-	cbz	x2, 2f
+	cbz	x2, 3f
 
 	mrs	x2, icc_sre_el2
 	orr	x2, x2, #ICC_SRE_EL2_EN	/* Enable access from insecure EL1 */
 	orr	x2, x2, #ICC_SRE_EL2_SRE	/* Enable system registers */
 	msr	icc_sre_el2, x2
-2:
+3:
 
 	/* Set the address to return to our return address */
 	msr	elr_el2, x30
diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h
index e3bdd83e8a29..15fc36014626 100644
--- a/sys/arm64/include/hypervisor.h
+++ b/sys/arm64/include/hypervisor.h
@@ -132,6 +132,41 @@
 #define	HCR_TWEDEn			(UL(0x1) << 59)
 #define	HCR_TWEDEL_MASK			(UL(0xf) << 60)
 
+/* HCRX_EL2 - Extended Hypervisor Configuration Register */
+#define HCRX_EL2_REG		MRS_REG_ALT_NAME(HCRX_EL2)
+#define HCRX_EL2_op0		3
+#define HCRX_EL2_op1		4
+#define HCRX_EL2_CRn		1
+#define HCRX_EL2_CRm		2
+#define HCRX_EL2_op2		2
+
+#define HCRX_EnAS0			(UL(0x1) << 0)
+#define HCRX_EnALS			(UL(0x1) << 1)
+#define HCRX_EnASR			(UL(0x1) << 2)
+#define HCRX_FnXS			(UL(0x1) << 3)
+#define HCRX_FGTnXS			(UL(0x1) << 4)
+#define HCRX_SMPME			(UL(0x1) << 5)
+#define HCRX_TALLINT			(UL(0x1) << 6)
+#define HCRX_VINMI			(UL(0x1) << 7)
+#define HCRX_VFNMI			(UL(0x1) << 8)
+#define HCRX_CMOW			(UL(0x1) << 9)
+#define HCRX_MCE2			(UL(0x1) << 10)
+#define HCRX_MSCEn			(UL(0x1) << 11)
+/* Bits 12 & 13 are reserved */
+#define HCRX_TCR2En			(UL(0x1) << 14)
+#define HCRX_SCTLR2En			(UL(0x1) << 15)
+#define HCRX_PTTWI			(UL(0x1) << 16)
+#define HCRX_D128En			(UL(0x1) << 17)
+#define HCRX_EnSNERR			(UL(0x1) << 18)
+#define HCRX_TMEA			(UL(0x1) << 19)
+#define HCRX_EnSDERR			(UL(0x1) << 20)
+#define HCRX_EnIDCP128			(UL(0x1) << 21)
+#define HCRX_GCSEn			(UL(0x1) << 22)
+#define HCRX_EnFPM			(UL(0x1) << 23)
+#define HCRX_PACMEn			(UL(0x1) << 24)
+/* Bit 25 is reserved */
+#define HCRX_SRMASKEn			(UL(0x1) << 26)
+
 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */
 #define	HPFAR_EL2_FIPA_SHIFT	4
 #define	HPFAR_EL2_FIPA_MASK	0xfffffffff0