git: d6d860c7ff5c - main - arm64: Add MRS_REG_ALT_NAME ID register macros

From: Andrew Turner <andrew_at_FreeBSD.org>
Date: Fri, 17 May 2024 10:21:54 UTC
The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=d6d860c7ff5c4cbe9475d98000407d6f0ea84b47

commit d6d860c7ff5c4cbe9475d98000407d6f0ea84b47
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2024-05-13 13:58:45 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2024-05-17 09:38:17 +0000

    arm64: Add MRS_REG_ALT_NAME ID register macros
    
    These can be used even when the compiler is too old for the register
    to be included.
    
    Reviewed by:    Zachary Leaf <zachary.leaf@arm.com>
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D45176
---
 sys/arm64/include/armreg.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 9391b1e2c1b7..5d193af5fd71 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -491,6 +491,7 @@
 
 /* ID_AA64AFR0_EL1 */
 #define	ID_AA64AFR0_EL1			MRS_REG(ID_AA64AFR0_EL1)
+#define	ID_AA64AFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64AFR0_EL1)
 #define	ID_AA64AFR0_EL1_op0		3
 #define	ID_AA64AFR0_EL1_op1		0
 #define	ID_AA64AFR0_EL1_CRn		0
@@ -499,6 +500,7 @@
 
 /* ID_AA64AFR1_EL1 */
 #define	ID_AA64AFR1_EL1			MRS_REG(ID_AA64AFR1_EL1)
+#define	ID_AA64AFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64AFR1_EL1)
 #define	ID_AA64AFR1_EL1_op0		3
 #define	ID_AA64AFR1_EL1_op1		0
 #define	ID_AA64AFR1_EL1_CRn		0
@@ -507,6 +509,7 @@
 
 /* ID_AA64DFR0_EL1 */
 #define	ID_AA64DFR0_EL1			MRS_REG(ID_AA64DFR0_EL1)
+#define	ID_AA64DFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64DFR0_EL1)
 #define	ID_AA64DFR0_EL1_op0		3
 #define	ID_AA64DFR0_EL1_op1		0
 #define	ID_AA64DFR0_EL1_CRn		0
@@ -596,6 +599,7 @@
 
 /* ID_AA64DFR1_EL1 */
 #define	ID_AA64DFR1_EL1			MRS_REG(ID_AA64DFR1_EL1)
+#define	ID_AA64DFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64DFR1_EL1)
 #define	ID_AA64DFR1_EL1_op0		3
 #define	ID_AA64DFR1_EL1_op1		0
 #define	ID_AA64DFR1_EL1_CRn		0
@@ -604,6 +608,7 @@
 
 /* ID_AA64ISAR0_EL1 */
 #define	ID_AA64ISAR0_EL1		MRS_REG(ID_AA64ISAR0_EL1)
+#define	ID_AA64ISAR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1)
 #define	ID_AA64ISAR0_EL1_op0		3
 #define	ID_AA64ISAR0_EL1_op1		0
 #define	ID_AA64ISAR0_EL1_CRn		0
@@ -690,6 +695,7 @@
 
 /* ID_AA64ISAR1_EL1 */
 #define	ID_AA64ISAR1_EL1		MRS_REG(ID_AA64ISAR1_EL1)
+#define	ID_AA64ISAR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1)
 #define	ID_AA64ISAR1_EL1_op0		3
 #define	ID_AA64ISAR1_EL1_op1		0
 #define	ID_AA64ISAR1_EL1_CRn		0
@@ -791,6 +797,7 @@
 
 /* ID_AA64ISAR2_EL1 */
 #define	ID_AA64ISAR2_EL1		MRS_REG(ID_AA64ISAR2_EL1)
+#define	ID_AA64ISAR2_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1)
 #define	ID_AA64ISAR2_EL1_op0		3
 #define	ID_AA64ISAR2_EL1_op1		0
 #define	ID_AA64ISAR2_EL1_CRn		0
@@ -838,6 +845,7 @@
 
 /* ID_AA64MMFR0_EL1 */
 #define	ID_AA64MMFR0_EL1		MRS_REG(ID_AA64MMFR0_EL1)
+#define	ID_AA64MMFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1)
 #define	ID_AA64MMFR0_EL1_op0		3
 #define	ID_AA64MMFR0_EL1_op1		0
 #define	ID_AA64MMFR0_EL1_CRn		0
@@ -929,6 +937,7 @@
 
 /* ID_AA64MMFR1_EL1 */
 #define	ID_AA64MMFR1_EL1		MRS_REG(ID_AA64MMFR1_EL1)
+#define	ID_AA64MMFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1)
 #define	ID_AA64MMFR1_EL1_op0		3
 #define	ID_AA64MMFR1_EL1_op1		0
 #define	ID_AA64MMFR1_EL1_CRn		0
@@ -1016,6 +1025,7 @@
 
 /* ID_AA64MMFR2_EL1 */
 #define	ID_AA64MMFR2_EL1		MRS_REG(ID_AA64MMFR2_EL1)
+#define	ID_AA64MMFR2_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1)
 #define	ID_AA64MMFR2_EL1_op0		3
 #define	ID_AA64MMFR2_EL1_op1		0
 #define	ID_AA64MMFR2_EL1_CRn		0
@@ -1102,6 +1112,7 @@
 
 /* ID_AA64MMFR3_EL1 */
 #define	ID_AA64MMFR3_EL1		MRS_REG(ID_AA64MMFR3_EL1)
+#define	ID_AA64MMFR3_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1)
 #define	ID_AA64MMFR3_EL1_op0		3
 #define	ID_AA64MMFR3_EL1_op1		0
 #define	ID_AA64MMFR3_EL1_CRn		0
@@ -1130,6 +1141,7 @@
 
 /* ID_AA64MMFR4_EL1 */
 #define	ID_AA64MMFR4_EL1		MRS_REG(ID_AA64MMFR4_EL1)
+#define	ID_AA64MMFR4_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1)
 #define	ID_AA64MMFR4_EL1_op0		3
 #define	ID_AA64MMFR4_EL1_op1		0
 #define	ID_AA64MMFR4_EL1_CRn		0
@@ -1138,6 +1150,7 @@
 
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
+#define	ID_AA64PFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64PFR0_EL1)
 #define	ID_AA64PFR0_EL1_op0		3
 #define	ID_AA64PFR0_EL1_op1		0
 #define	ID_AA64PFR0_EL1_CRn		0
@@ -1236,6 +1249,7 @@
 
 /* ID_AA64PFR1_EL1 */
 #define	ID_AA64PFR1_EL1			MRS_REG(ID_AA64PFR1_EL1)
+#define	ID_AA64PFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64PFR1_EL1)
 #define	ID_AA64PFR1_EL1_op0		3
 #define	ID_AA64PFR1_EL1_op1		0
 #define	ID_AA64PFR1_EL1_CRn		0
@@ -1294,6 +1308,7 @@
 
 /* ID_AA64PFR2_EL1 */
 #define	ID_AA64PFR2_EL1			MRS_REG(ID_AA64PFR2_EL1)
+#define	ID_AA64PFR2_EL1_REG		MRS_REG_ALT_NAME(ID_AA64PFR2_EL1)
 #define	ID_AA64PFR2_EL1_op0		3
 #define	ID_AA64PFR2_EL1_op1		0
 #define	ID_AA64PFR2_EL1_CRn		0