git: 634dd430b966 - main - arm64: Update the page table list in locore

The branch main has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=634dd430b966405f7bd9c2d647b0d7c1281c3de9

commit 634dd430b966405f7bd9c2d647b0d7c1281c3de9
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2024-04-24 10:23:42 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2024-05-10 09:29:24 +0000

    arm64: Update the page table list in locore
    
    The comment describing the page tables was out of date. Update it with
    the current list.
    
    Sponsored by:   Arm Ltd
---
 sys/arm64/arm64/locore.S | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S
index 67bdece402c2..f53cd365de55 100644
--- a/sys/arm64/arm64/locore.S
+++ b/sys/arm64/arm64/locore.S
@@ -429,14 +429,16 @@ LEND(get_load_phys_addr)
  *  All the memory must not cross a 1GiB boundaty
  *  x28 contains the physical address we were loaded from
  *
- * TODO: This is out of date.
- *  There are at least 5 pages before that address for the page tables
+ *  There are 7 or 8 pages before that address for the page tables
  *   The pages used are:
+ *    - The Kernel L3 tables (only for 16k kernel)
  *    - The Kernel L2 table
  *    - The Kernel L1 table
  *    - The Kernel L0 table             (TTBR1)
+ *    - The identity (PA = VA) L2 table
  *    - The identity (PA = VA) L1 table
- *    - The identity (PA = VA) L0 table (TTBR0)
+ *    - The identity (PA = VA) L0 table (Early TTBR0)
+ *    - The Kernel empty L0 table       (Late TTBR0)
  */
 LENTRY(create_pagetables)
 	/* Save the Link register */