git: 312a05c39e5f - main - riscv: remove more riscv64sf support

The branch main has been updated by brooks:

URL: https://cgit.FreeBSD.org/src/commit/?id=312a05c39e5fd79b37ee6f922462232797f56a2a

commit 312a05c39e5fd79b37ee6f922462232797f56a2a
Author:     Brooks Davis <brooks@FreeBSD.org>
AuthorDate: 2024-03-21 23:46:28 +0000
Commit:     Brooks Davis <brooks@FreeBSD.org>
CommitDate: 2024-03-21 23:48:37 +0000

    riscv: remove more riscv64sf support
    
    Remove a few more bits of riscv64sf support in libc and libm.
    
    Reduce floating point ABI checks to requiring double hard float.
    
    Reviewed by:    imp, jhb
    Fixes:          1ca12bd927d7 Remove the riscv64sf architecture.
    Differential Revision:  https://reviews.freebsd.org/D44334
---
 lib/libc/riscv/gen/flt_rounds.c | 10 ----------
 lib/msun/riscv/Symbol.map       |  1 -
 lib/msun/riscv/fenv.c           |  8 --------
 lib/msun/riscv/fenv.h           | 30 ++----------------------------
 4 files changed, 2 insertions(+), 47 deletions(-)

diff --git a/lib/libc/riscv/gen/flt_rounds.c b/lib/libc/riscv/gen/flt_rounds.c
index 5d3771ea6cd3..bccd7d8baa44 100644
--- a/lib/libc/riscv/gen/flt_rounds.c
+++ b/lib/libc/riscv/gen/flt_rounds.c
@@ -37,22 +37,12 @@
 #include <fenv.h>
 #include <float.h>
 
-#ifdef __riscv_float_abi_soft
-#include "softfloat-for-gcc.h"
-#include "milieu.h"
-#include "softfloat.h"
-#endif
-
 int
 __flt_rounds(void)
 {
 	uint64_t mode;
 
-#ifdef __riscv_float_abi_soft
-	mode = __softfloat_float_rounding_mode;
-#else
 	__asm __volatile("csrr %0, fcsr" : "=r" (mode));
-#endif
 
 	switch (mode & _ROUND_MASK) {
 	case FE_TOWARDZERO:
diff --git a/lib/msun/riscv/Symbol.map b/lib/msun/riscv/Symbol.map
index c3d72443cb2c..65157d0de9c1 100644
--- a/lib/msun/riscv/Symbol.map
+++ b/lib/msun/riscv/Symbol.map
@@ -4,7 +4,6 @@ FBSD_1.3 {
 	fegetenv;
 	feholdexcept;
 	feupdateenv;
-	fegetexcept;
 };
 
 FBSD_1.8 {
diff --git a/lib/msun/riscv/fenv.c b/lib/msun/riscv/fenv.c
index 9d7ae3d3fdaf..a4dde02a6ddc 100644
--- a/lib/msun/riscv/fenv.c
+++ b/lib/msun/riscv/fenv.c
@@ -37,14 +37,6 @@
  */
 const fenv_t __fe_dfl_env = 0;
 
-#ifdef __riscv_float_abi_soft
-#define __set_env(env, flags, mask, rnd) env = ((flags) | (rnd) << 5)
-#define __env_flags(env)                ((env) & FE_ALL_EXCEPT)
-#define __env_mask(env)                 (0) /* No exception traps. */
-#define __env_round(env)                (((env) >> 5) & _ROUND_MASK)
-#include "fenv-softfloat.h"
-#endif
-
 extern inline int feclearexcept(int __excepts);
 extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
 extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
diff --git a/lib/msun/riscv/fenv.h b/lib/msun/riscv/fenv.h
index 36abb7b00b7d..cc50f0659248 100644
--- a/lib/msun/riscv/fenv.h
+++ b/lib/msun/riscv/fenv.h
@@ -71,32 +71,13 @@ __BEGIN_DECLS
 extern const fenv_t	__fe_dfl_env;
 #define	FE_DFL_ENV	(&__fe_dfl_env)
 
-#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double)
-#if defined(__riscv_float_abi_single)
-#error single precision floating point ABI not supported
-#else
-#error compiler did not set soft/hard float macros
-#endif
+#ifndef __riscv_float_abi_double
+#error only double hard float ABI supported
 #endif
 
-#ifndef __riscv_float_abi_soft
 #define	__rfs(__fcsr)	__asm __volatile("csrr %0, fcsr" : "=r" (__fcsr))
 #define	__wfs(__fcsr)	__asm __volatile("csrw fcsr, %0" :: "r" (__fcsr))
-#endif
 
-#ifdef __riscv_float_abi_soft
-int feclearexcept(int __excepts);
-int fegetexceptflag(fexcept_t *__flagp, int __excepts);
-int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
-int feraiseexcept(int __excepts);
-int fetestexcept(int __excepts);
-int fegetround(void);
-int fesetround(int __round);
-int fegetenv(fenv_t *__envp);
-int feholdexcept(fenv_t *__envp);
-int fesetenv(const fenv_t *__envp);
-int feupdateenv(const fenv_t *__envp);
-#else
 __fenv_static inline int
 feclearexcept(int __excepts)
 {
@@ -212,15 +193,9 @@ feupdateenv(const fenv_t *__envp)
 
 	return (0);
 }
-#endif /* !__riscv_float_abi_soft */
 
 #if __BSD_VISIBLE
 
-#ifdef __riscv_float_abi_soft
-int feenableexcept(int __mask);
-int fedisableexcept(int __mask);
-int fegetexcept(void);
-#else
 __fenv_static inline int
 feenableexcept(int __mask __unused)
 {
@@ -248,7 +223,6 @@ fegetexcept(void)
 
 	return (0);
 }
-#endif /* !__riscv_float_abi_soft */
 
 #endif /* __BSD_VISIBLE */