git: 2b5827fbbae7 - stable/13 - arm64: Decode the ID_AA64MMFR4_EL1 register

The branch stable/13 has been updated by andrew:

URL: https://cgit.FreeBSD.org/src/commit/?id=2b5827fbbae7b7de96221e966d8f676560120084

commit 2b5827fbbae7b7de96221e966d8f676560120084
Author:     Andrew Turner <andrew@FreeBSD.org>
AuthorDate: 2023-07-06 13:51:52 +0000
Commit:     Andrew Turner <andrew@FreeBSD.org>
CommitDate: 2024-07-15 08:09:50 +0000

    arm64: Decode the ID_AA64MMFR4_EL1 register
    
    No fields have been defined, but it has been documented in the
    Architecture Reference Manual.
    
    Sponsored by:   Arm Ltd
    Differential Revision:  https://reviews.freebsd.org/D40894
    
    (cherry picked from commit 22235b631ba27d71090aa8f0d2794395feddbbe6)
---
 sys/arm64/arm64/identcpu.c | 14 ++++++++++++++
 sys/arm64/include/armreg.h |  8 ++++++++
 2 files changed, 22 insertions(+)

diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c
index 2750f400fb66..02dcfa326559 100644
--- a/sys/arm64/arm64/identcpu.c
+++ b/sys/arm64/arm64/identcpu.c
@@ -130,6 +130,7 @@ struct cpu_desc {
 	uint64_t	id_aa64mmfr1;
 	uint64_t	id_aa64mmfr2;
 	uint64_t	id_aa64mmfr3;
+	uint64_t	id_aa64mmfr4;
 	uint64_t	id_aa64pfr0;
 	uint64_t	id_aa64pfr1;
 	uint64_t	id_aa64zfr0;
@@ -1243,6 +1244,12 @@ static const struct mrs_field id_aa64mmfr3_fields[] = {
 };
 
 
+/* ID_AA64MMFR4_EL1 */
+static const struct mrs_field id_aa64mmfr4_fields[] = {
+	MRS_FIELD_END,
+};
+
+
 /* ID_AA64PFR0_EL1 */
 static const struct mrs_field_value id_aa64pfr0_csv3[] = {
 	MRS_FIELD_VALUE(ID_AA64PFR0_CSV3_NONE, ""),
@@ -1780,6 +1787,7 @@ static const struct mrs_user_reg user_regs[] = {
 	USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1),
 	USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2),
 	USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3),
+	USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4),
 
 	USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0),
 	USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1),
@@ -2481,6 +2489,11 @@ print_cpu_features(u_int cpu)
 		print_id_register(sb, "Memory Model Features 3",
 		    cpu_desc[cpu].id_aa64mmfr3, id_aa64mmfr3_fields);
 
+	/* AArch64 Memory Model Feature Register 4 */
+	if (SHOULD_PRINT_REG(id_aa64mmfr4))
+		print_id_register(sb, "Memory Model Features 4",
+		    cpu_desc[cpu].id_aa64mmfr4, id_aa64mmfr4_fields);
+
 	/* AArch64 Debug Feature Register 0 */
 	if (SHOULD_PRINT_REG(id_aa64dfr0))
 		print_id_register(sb, "Debug Features 0",
@@ -2594,6 +2607,7 @@ identify_cpu(u_int cpu)
 	cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
 	cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
 	cpu_desc[cpu].id_aa64mmfr3 = READ_SPECIALREG(id_aa64mmfr3_el1);
+	cpu_desc[cpu].id_aa64mmfr4 = READ_SPECIALREG(id_aa64mmfr4_el1);
 	cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
 	cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
 
diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
index 1a5863b82535..4f99f50456ef 100644
--- a/sys/arm64/include/armreg.h
+++ b/sys/arm64/include/armreg.h
@@ -1116,6 +1116,14 @@
 #define	 ID_AA64MMFR3_Spec_FPACC_NONE	(UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
 #define	 ID_AA64MMFR3_Spec_FPACC_IMPL	(UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
 
+/* ID_AA64MMFR4_EL1 */
+#define	ID_AA64MMFR4_EL1		MRS_REG(ID_AA64MMFR4_EL1)
+#define	ID_AA64MMFR4_EL1_op0		3
+#define	ID_AA64MMFR4_EL1_op1		0
+#define	ID_AA64MMFR4_EL1_CRn		0
+#define	ID_AA64MMFR4_EL1_CRm		7
+#define	ID_AA64MMFR4_EL1_op2		4
+
 /* ID_AA64PFR0_EL1 */
 #define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
 #define	ID_AA64PFR0_EL1_op0		3