git: 1fc6f25daf30 - stable/14 - x86: Refactor pcie_cfgregopen

The branch stable/14 has been updated by jhb:

URL: https://cgit.FreeBSD.org/src/commit/?id=1fc6f25daf301a876a543ff86842e23fc1cc9830

commit 1fc6f25daf301a876a543ff86842e23fc1cc9830
Author:     John Baldwin <jhb@FreeBSD.org>
AuthorDate: 2023-11-29 18:32:16 +0000
Commit:     John Baldwin <jhb@FreeBSD.org>
CommitDate: 2024-01-18 23:23:32 +0000

    x86: Refactor pcie_cfgregopen
    
    Split out some bits of pcie_cfgregopen that only need to be executed
    once into helper functions in preparation for supporting multiple MCFG
    entries.
    
    Reviewed by:    imp
    Differential Revision:  https://reviews.freebsd.org/D42829
    
    (cherry picked from commit 9893a4fd31fa4b2e19a7b9cf786f49b9de50b407)
---
 sys/amd64/pci/pci_cfgreg.c | 43 +++++++++++++++-----------
 sys/i386/pci/pci_cfgreg.c  | 75 ++++++++++++++++++++++++++++------------------
 2 files changed, 71 insertions(+), 47 deletions(-)

diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c
index 6b95c6fae0ab..dd177b6e9a8c 100644
--- a/sys/amd64/pci/pci_cfgreg.c
+++ b/sys/amd64/pci/pci_cfgreg.c
@@ -218,28 +218,12 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
 	mtx_unlock_spin(&pcicfg_mtx);
 }
 
-int
-pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
+static void
+pcie_init_badslots(void)
 {
 	uint32_t val1, val2;
 	int slot;
 
-	if (!mcfg_enable)
-		return (0);
-
-	if (minbus != 0)
-		return (0);
-
-	if (bootverbose)
-		printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
-		    base);
-
-	/* XXX: We should make sure this really fits into the direct map. */
-	pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20);
-	pcie_minbus = minbus;
-	pcie_maxbus = maxbus;
-	cfgmech = CFGMECH_PCIE;
-
 	/*
 	 * On some AMD systems, some of the devices on bus 0 are
 	 * inaccessible using memory-mapped PCI config access.  Walk
@@ -257,6 +241,29 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
 				pcie_badslots |= (1 << slot);
 		}
 	}
+}
+
+int
+pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
+{
+
+	if (!mcfg_enable)
+		return (0);
+
+	if (minbus != 0)
+		return (0);
+
+	if (bootverbose)
+		printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
+		    base);
+
+	/* XXX: We should make sure this really fits into the direct map. */
+	pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20);
+	pcie_minbus = minbus;
+	pcie_maxbus = maxbus;
+	cfgmech = CFGMECH_PCIE;
+
+	pcie_init_badslots();
 
 	return (1);
 }
diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c
index ef712fe49fe3..2129782063d3 100644
--- a/sys/i386/pci/pci_cfgreg.c
+++ b/sys/i386/pci/pci_cfgreg.c
@@ -437,8 +437,8 @@ pcireg_cfgopen(void)
 	return (cfgmech);
 }
 
-int
-pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
+static bool
+pcie_init_cache(void)
 {
 	struct pcie_cfg_list *pcielist;
 	struct pcie_cfg_elem *pcie_array, *elem;
@@ -446,26 +446,7 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
 	struct pcpu *pc;
 #endif
 	vm_offset_t va;
-	uint32_t val1, val2;
-	int i, slot;
-
-	if (!mcfg_enable)
-		return (0);
-
-	if (minbus != 0)
-		return (0);
-
-	if (!pae_mode && base >= 0x100000000) {
-		if (bootverbose)
-			printf(
-	    "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
-			    (uintmax_t)base);
-		return (0);
-	}
-		
-	if (bootverbose)
-		printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
-		    (uintmax_t)base);
+	int i;
 
 #ifdef SMP
 	STAILQ_FOREACH(pc, &cpuhead, pc_allcpu)
@@ -474,12 +455,12 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
 		pcie_array = malloc(sizeof(struct pcie_cfg_elem) * PCIE_CACHE,
 		    M_DEVBUF, M_NOWAIT);
 		if (pcie_array == NULL)
-			return (0);
+			return (false);
 
 		va = kva_alloc(PCIE_CACHE * PAGE_SIZE);
 		if (va == 0) {
 			free(pcie_array, M_DEVBUF);
-			return (0);
+			return (false);
 		}
 
 #ifdef SMP
@@ -495,12 +476,14 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
 			TAILQ_INSERT_HEAD(pcielist, elem, elem);
 		}
 	}
+	return (true);
+}
 
-	pcie_base = base;
-	pcie_minbus = minbus;
-	pcie_maxbus = maxbus;
-	cfgmech = CFGMECH_PCIE;
-	devmax = 32;
+static void
+pcie_init_badslots(void)
+{
+	uint32_t val1, val2;
+	int slot;
 
 	/*
 	 * On some AMD systems, some of the devices on bus 0 are
@@ -519,6 +502,40 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
 				pcie_badslots |= (1 << slot);
 		}
 	}
+}
+
+int
+pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
+{
+
+	if (!mcfg_enable)
+		return (0);
+
+	if (minbus != 0)
+		return (0);
+
+	if (!pae_mode && base >= 0x100000000) {
+		if (bootverbose)
+			printf(
+	    "PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
+			    (uintmax_t)base);
+		return (0);
+	}
+
+	if (bootverbose)
+		printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
+		    (uintmax_t)base);
+
+	if (!pcie_init_cache())
+		return (0);
+
+	pcie_base = base;
+	pcie_minbus = minbus;
+	pcie_maxbus = maxbus;
+	cfgmech = CFGMECH_PCIE;
+	devmax = 32;
+
+	pcie_init_badslots();
 
 	return (1);
 }