git: d3b05d0ea10a - main - Add smbus and i2c device IDs for Meteor Lake
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Date: Tue, 13 Aug 2024 12:55:38 UTC
The branch main has been updated by lwhsu: URL: https://cgit.FreeBSD.org/src/commit/?id=d3b05d0ea10abe059dc63c6fb6ef3f061b758af2 commit d3b05d0ea10abe059dc63c6fb6ef3f061b758af2 Author: SHENG-YI HONG <aokblast@FreeBSD.org> AuthorDate: 2024-08-13 12:22:43 +0000 Commit: Li-Wen Hsu <lwhsu@FreeBSD.org> CommitDate: 2024-08-13 12:52:19 +0000 Add smbus and i2c device IDs for Meteor Lake Reviewed by: emaste, Daniel Schaefer <dhs@frame.work> MFC after: 3 days Sponsored by: Framework Computer Inc Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D46249 --- sys/dev/ichiic/ig4_pci.c | 8 ++++++++ sys/dev/ichsmb/ichsmb_pci.c | 9 +++++++++ 2 files changed, 17 insertions(+) diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c index 9f12e713cdeb..138de77c35db 100644 --- a/sys/dev/ichiic/ig4_pci.c +++ b/sys/dev/ichiic/ig4_pci.c @@ -168,6 +168,10 @@ static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_ALDERLAKE_M_I2C_3 0x54eb8086 #define PCI_CHIP_ALDERLAKE_M_I2C_4 0x54c58086 #define PCI_CHIP_ALDERLAKE_M_I2C_5 0x54c68086 +#define PCI_CHIP_METEORLAKE_M_I2C_0 0x7e788086 +#define PCI_CHIP_METEORLAKE_M_I2C_1 0x7e798086 +#define PCI_CHIP_METEORLAKE_M_I2C_2 0x7e508086 +#define PCI_CHIP_METEORLAKE_M_I2C_3 0x7e518086 struct ig4iic_pci_device { uint32_t devid; @@ -280,6 +284,10 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] = { { PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4", IG4_TIGERLAKE}, { PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_0, "Intel Meteor Lake-M I2C Controller-0", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_1, "Intel Meteor Lake-M I2C Controller-1", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_2, "Intel Meteor Lake-M I2C Controller-2", IG4_TIGERLAKE}, + { PCI_CHIP_METEORLAKE_M_I2C_3, "Intel Meteor Lake-M I2C Controller-3", IG4_TIGERLAKE}, }; static int diff --git a/sys/dev/ichsmb/ichsmb_pci.c b/sys/dev/ichsmb/ichsmb_pci.c index 675a15daaf1b..728bb942d503 100644 --- a/sys/dev/ichsmb/ichsmb_pci.c +++ b/sys/dev/ichsmb/ichsmb_pci.c @@ -113,6 +113,9 @@ #define ID_ALDERLAKE 0x7aa3 #define ID_ALDERLAKE2 0x51a3 #define ID_ALDERLAKE3 0x54a3 +#define ID_METEORLAKE 0x7e22 +#define ID_METEORLAKE2 0x7f23 +#define ID_METEORLAKE3 0xae22 static const struct pci_device_table ichsmb_devices[] = { { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA), @@ -215,6 +218,12 @@ static const struct pci_device_table ichsmb_devices[] = { PCI_DESCR("Intel Alder Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3), PCI_DESCR("Intel Alder Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE), + PCI_DESCR("Intel Meteor Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE2), + PCI_DESCR("Intel Meteor Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_METEORLAKE3), + PCI_DESCR("Intel Meteor Lake SMBus controller") }, }; /* Internal functions */