git: 7f156d86dfa9 - stable/14 - tegra210: change to UTF-8 (from ISO-8859)

The branch stable/14 has been updated by emaste:

URL: https://cgit.FreeBSD.org/src/commit/?id=7f156d86dfa9d40ddf7e389c502a743f7d0439a8

commit 7f156d86dfa9d40ddf7e389c502a743f7d0439a8
Author:     Ed Maste <emaste@FreeBSD.org>
AuthorDate: 2023-12-29 03:53:16 +0000
Commit:     Ed Maste <emaste@FreeBSD.org>
CommitDate: 2024-04-16 13:57:43 +0000

    tegra210: change to UTF-8 (from ISO-8859)
    
    Prompted by Phabricator's complaint that a C source file was a binary
    file, in D43192.
    
    Reviewed by:    mmel
    Differential Revision: https://reviews.freebsd.org/D43229
    
    (cherry picked from commit 56c202de785a5701831ae345a1a5c906e0b2c3e6)
---
 sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c b/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
index c3ebb4622081..726f26c9f9b5 100644
--- a/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
+++ b/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
@@ -656,7 +656,7 @@ uphy_pex_enable(struct padctl_softc *sc, struct padctl_pad *pad)
 		goto err;
 	}
 
-	/* 5. Enable the PLL (20 µs Lock time) */
+	/* 5. Enable the PLL (20 μs Lock time) */
 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 	reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE;
 	WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg);
@@ -891,7 +891,7 @@ uphy_sata_enable(struct padctl_softc *sc, struct padctl_pad *pad, bool usb)
 		goto err;
 	}
 
-	/* 5. Enable the PLL (20 µs Lock time) */
+	/* 5. Enable the PLL (20 μs Lock time) */
 	reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 	reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE;
 	WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);