From nobody Thu May 25 17:06:33 2023 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4QRvbY4bg3z4WS5c; Thu, 25 May 2023 17:06:33 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4QRvbY3tF1z3kmp; Thu, 25 May 2023 17:06:33 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1685034393; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=oLWboI9LFnSgy7tMEYVFs6qNR/yaSfCLL+6Tw39qWfQ=; b=Lla8UQfd9IkIh/FSu+C/auZKHqlNsgP7pg0GtqAl5ogk6nvEnz0g61V+q0Sbr5pFuK7CC8 tZqtukNuar8xEcZ+WwNrauWABdcUnGvXty9rQMx3ITmLDX5YoxhfCVca7+5Xx1zP+m6+KU FvOczc430U65fKbrrI38CFxR65gDq32yLHUwb2CNpMDwZsvcZ4FmKUh2nZ6cskFg15Ljey 1e/9G+g9+iibwPF424pZ9rZI59JQ6TEmwNWXxha6cV/TGZp25Z0QtdlvxgiUpltgG9Z7LT XnyQWvQz9WNUqe5xg4OLv16l9QAdawTQAoJ53zqxY9CFwnfmyBlCFDsDFzSRTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1685034393; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=oLWboI9LFnSgy7tMEYVFs6qNR/yaSfCLL+6Tw39qWfQ=; b=Hn4pL2Pxr02yQzwptNzisxHyILrbgE3nFmHYwFDpi+rQWC2nZ/YXdZeJwrnixtLDnaxXfg dHOKg77K+6HtgS6RLTvfla+fnkxD11gcOmxGiae2vEH2xQoIe9oEh0SluR1PokgYs2TmMF UQLag1b0qEgiidi7nY4Y6ug8BrPSMwH8sIwb4C0YXaTgqrJN1mSuOi5FnVd5Yy3RWiYUUx 3jEdC3lBSYU8a2vGbEVLqGihFyL6pl++iIZy5tjwqntM7bTEzGGaYzhR1Fy/+TWdbzzBrd UTF51dPMSROXPfdP+A4QAVbg4wm612G4X/tEYx9K7qA9rTC8+o8gU1F4v+xWEw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1685034393; a=rsa-sha256; cv=none; b=j55jrv5l2Jfrzk45dZ37xjdUT6hLWcLVNCsFJhTPj+b3PMah//1gUKlbK63U8UOBwCNAPp jID0KFaOygh88lNoJcg+y8S2x2JgoVfFhF8AihNLk+AQykZ/PJ6Xmf67tkZtQN/t8TQtZk o2/RV62dhu4+lkxxFnwJdGRTBT7/2OodBPVP8G5qPiQUX3f84k6kijoLbyy5yAvrHVxuDw 3QicjBfcJDkgCa4rD39CGkkiP4XM6p7ldUqxzwU9WJq2mvw/30hKJDs595O1WxI4QsA1w7 tRRb3pAg8FOZQBWZlB/ZUIORKInPdWIZ2r095fBO6ZQweS2bPD0JzJmGUqpB1w== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4QRvbY2gDYzYNg; Thu, 25 May 2023 17:06:33 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 34PH6Xrr028019; Thu, 25 May 2023 17:06:33 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 34PH6XNm028018; Thu, 25 May 2023 17:06:33 GMT (envelope-from git) Date: Thu, 25 May 2023 17:06:33 GMT Message-Id: <202305251706.34PH6XNm028018@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: ffa75b573f04 - main - arm64/disassem.c: Add shifted register instruction definitions List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: ffa75b573f043951c7958c200c1e0e1b1f703740 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=ffa75b573f043951c7958c200c1e0e1b1f703740 commit ffa75b573f043951c7958c200c1e0e1b1f703740 Author: Mykola Hohsadze AuthorDate: 2023-05-25 14:41:55 +0000 Commit: Mitchell Horne CommitDate: 2023-05-25 17:06:15 +0000 arm64/disassem.c: Add shifted register instruction definitions Add disassembly support for the following shifted register instructions: * adds * subs * sub * neg * negs * cmp * cmn The 'Mandatory Tokens' checks are relaxed to allow for the alias instructions (e.g. cmp) which hard-code one or more registers as xzr. Reviewed by: mhorne MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D40006 --- sys/arm64/arm64/disassem.c | 58 +++++++++++++++++++++++++++++++++------------- 1 file changed, 42 insertions(+), 16 deletions(-) diff --git a/sys/arm64/arm64/disassem.c b/sys/arm64/arm64/disassem.c index 2ec0d04d5491..f1a4f9206c1b 100644 --- a/sys/arm64/arm64/disassem.c +++ b/sys/arm64/arm64/disassem.c @@ -91,6 +91,8 @@ enum arm64_format_type { /* * OP , , {, #imm} SF32/64 * OP , , #{, } SF32/64 + * OP , {, # } + * OP , {, # } */ TYPE_01, @@ -151,6 +153,10 @@ static struct arm64_insn arm64_i[] = { TYPE_01, OP_RD_SP | OP_RN_SP }, /* mov (to/from sp) */ { "add", "SF(1)|0010001|SHIFT(2)|IMM(12)|RN(5)|RD(5)", TYPE_01, OP_RD_SP | OP_RN_SP }, /* add immediate */ + { "cmn", "SF(1)|0101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|11111", + TYPE_01, 0 }, /* cmn shifted register */ + { "adds", "SF(1)|0101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, 0 }, /* adds shifted register */ { "ldr", "1|SF(1)|111000010|IMM(9)|OPTION(2)|RN(5)|RT(5)", TYPE_02, OP_SIGN_EXT | OP_RN_SP }, /* ldr immediate post/pre index */ { "ldr", "1|SF(1)|11100101|IMM(12)|RN(5)|RT(5)", @@ -216,6 +222,16 @@ static struct arm64_insn arm64_i[] = { { "strh", "01111000001|RM(5)|OPTION(3)|SCALE(1)|10|RN(5)|RT(5)", TYPE_02, OP_SF32 | OP_RN_SP }, /* strh register */ + { "neg", "SF(1)|1001011|SHIFT(2)|0|RM(5)|IMM(6)|11111|RD(5)", + TYPE_01, 0 }, /* neg shifted register */ + { "sub", "SF(1)|1001011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, 0 }, /* sub shifted register */ + { "cmp", "SF(1)|1101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|11111", + TYPE_01, 0 }, /* cmp shifted register */ + { "negs", "SF(1)|1101011|SHIFT(2)|0|RM(5)|IMM(6)|11111|RD(5)", + TYPE_01, 0 }, /* negs shifted register */ + { "subs", "SF(1)|1101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", + TYPE_01, 0 }, /* subs shifted register */ { NULL, NULL } }; @@ -397,7 +413,7 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) int ret; int shift, rm, rt, rd, rn, imm, sf, idx, option, scale, amount; int sign_ext; - int rm_absent; + bool rm_absent, rd_absent, rn_absent; /* Indicate if immediate should be outside or inside brackets */ int inside; /* Print exclamation mark if pre-incremented */ @@ -454,27 +470,37 @@ disasm(const struct disasm_interface *di, vm_offset_t loc, int altfmt) /* * OP , , {, #} SF32/64 * OP , , #{, } SF32/64 + * OP , {, # } + * OP , {, # } */ - /* Mandatory tokens */ - ret = arm64_disasm_read_token(i_ptr, insn, "RD", &rd); - ret |= arm64_disasm_read_token(i_ptr, insn, "RN", &rn); - if (ret != 0) { - printf("ERROR: " - "Missing mandatory token for op %s type %d\n", - i_ptr->name, i_ptr->type); - goto undefined; - } - - /* Optional tokens */ - arm64_disasm_read_token(i_ptr, insn, "SHIFT", &shift); + rd_absent = arm64_disasm_read_token(i_ptr, insn, "RD", &rd); + rn_absent = arm64_disasm_read_token(i_ptr, insn, "RN", &rn); rm_absent = arm64_disasm_read_token(i_ptr, insn, "RM", &rm); + arm64_disasm_read_token(i_ptr, insn, "SHIFT", &shift); - di->di_printf("%s\t%s, %s", i_ptr->name, - arm64_reg(sf, rd, rd_sp), arm64_reg(sf, rn, rn_sp)); + di->di_printf("%s\t", i_ptr->name); + + /* + * If RD and RN are present, we will display the following + * patterns: + * - OP , , {, #} SF32/64 + * - OP , , #{, } SF32/64 + * Otherwise if only RD is present: + * - OP , {, # } + * Otherwise if only RN is present: + * - OP , {, # } + */ + if (!rd_absent && !rn_absent) + di->di_printf("%s, %s", arm64_reg(sf, rd, rd_sp), + arm64_reg(sf, rn, rn_sp)); + else if (!rd_absent) + di->di_printf("%s", arm64_reg(sf, rd, rd_sp)); + else + di->di_printf("%s", arm64_reg(sf, rn, rn_sp)); /* If RM is present use it, otherwise use immediate notation */ - if (rm_absent == 0) { + if (!rm_absent) { di->di_printf(", %s", arm64_reg(sf, rm, rm_sp)); if (imm != 0) di->di_printf(", %s #%d", shift_2[shift], imm);