git: 651e037e2720 - stable/13 - Intel DMAR: remove parsing of 6-level paging capability

The branch stable/13 has been updated by jah:

URL: https://cgit.FreeBSD.org/src/commit/?id=651e037e27207f94c50a3a07d78493c51065da64

commit 651e037e27207f94c50a3a07d78493c51065da64
Author:     Jason A. Harmening <jah@FreeBSD.org>
AuthorDate: 2023-05-01 16:22:39 +0000
Commit:     Jason A. Harmening <jah@FreeBSD.org>
CommitDate: 2023-05-06 00:58:41 +0000

    Intel DMAR: remove parsing of 6-level paging capability
    
    Early versions of the VT-d spec mentioned 6-level paging support as a
    possible value for the SAGAW capability, but later versions removed it
    and SAGAW=0x10 is currently listed as a reserved value.
    
    The 6-level (agaw=64) entry in sagaw_bits is furthermore problematic
    with clang15 because the attempted comparison against 1ULL << 64 in
    dmar_maxaddr2mgaw() causes the compiler to elide the last iteration
    of the initial loop, which bypasses the subsequent logic to find the
    greatest HW-supported address width.  This results in 5-level paging
    always being selected regardless of whether the hardware supports it,
    which can result address translation failure due to invalid context-
    entry programming.
    
    Reviewed by:    kib
    Differential Revision: https://reviews.freebsd.org/D39896
    
    (cherry picked from commit 6f378116e9bf982b8246d033d81cb64d52b24462)
---
 sys/x86/iommu/intel_utils.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/sys/x86/iommu/intel_utils.c b/sys/x86/iommu/intel_utils.c
index 152c7cac3a7d..315ffc8d4160 100644
--- a/sys/x86/iommu/intel_utils.c
+++ b/sys/x86/iommu/intel_utils.c
@@ -99,9 +99,14 @@ static const struct sagaw_bits_tag {
 	{.agaw = 48, .cap = DMAR_CAP_SAGAW_4LVL, .awlvl = DMAR_CTX2_AW_4LVL,
 	    .pglvl = 4},
 	{.agaw = 57, .cap = DMAR_CAP_SAGAW_5LVL, .awlvl = DMAR_CTX2_AW_5LVL,
-	    .pglvl = 5},
-	{.agaw = 64, .cap = DMAR_CAP_SAGAW_6LVL, .awlvl = DMAR_CTX2_AW_6LVL,
-	    .pglvl = 6}
+	    .pglvl = 5}
+	/*
+	 * 6-level paging (DMAR_CAP_SAGAW_6LVL) is not supported on any
+	 * current VT-d hardware and its SAGAW field value is listed as
+	 * reserved in the VT-d spec.  If support is added in the future,
+	 * this structure and the logic in dmar_maxaddr2mgaw() will need
+	 * to change to avoid attempted comparison against 1ULL << 64.
+	 */
 };
 
 bool