git: e59d202312f9 - main - arm64: make VM_NFREEORDER and the comment describing it match

From: Alan Cox <alc_at_FreeBSD.org>
Date: Thu, 29 Jun 2023 18:07:15 UTC
The branch main has been updated by alc:

URL: https://cgit.FreeBSD.org/src/commit/?id=e59d202312f9868583c6603030ded2476085920d

commit e59d202312f9868583c6603030ded2476085920d
Author:     Alan Cox <alc@FreeBSD.org>
AuthorDate: 2023-06-28 08:23:09 +0000
Commit:     Alan Cox <alc@FreeBSD.org>
CommitDate: 2023-06-29 17:48:48 +0000

    arm64: make VM_NFREEORDER and the comment describing it match
    
    The setting of VM_NFREEORDER and the comment describing it were copied
    from sparc64 where both the page size and the number of page table
    entries that fit in a cache line are different from arm64.
    
    Reviewed by:    andrew, kib, markj
    MFC after:      2 weeks
    Differential Revision:  https://reviews.freebsd.org/D40782
---
 sys/arm64/include/vmparam.h | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/sys/arm64/include/vmparam.h b/sys/arm64/include/vmparam.h
index b28a79256453..23b7d0d87c94 100644
--- a/sys/arm64/include/vmparam.h
+++ b/sys/arm64/include/vmparam.h
@@ -89,14 +89,15 @@
 #define	VM_FREELIST_DEFAULT	0
 
 /*
- * An allocation size of 16MB is supported in order to optimize the
- * use of the direct map by UMA.  Specifically, a cache line contains
- * at most four TTEs, collectively mapping 16MB of physical memory.
- * By reducing the number of distinct 16MB "pages" that are used by UMA,
- * the physical memory allocator reduces the likelihood of both 4MB
- * page TLB misses and cache misses caused by 4MB page TLB misses.
+ * When PAGE_SIZE is 4KB, an allocation size of 16MB is supported in order
+ * to optimize the use of the direct map by UMA.  Specifically, a 64-byte
+ * cache line contains at most 8 L2 BLOCK entries, collectively mapping 16MB
+ * of physical memory.  By reducing the number of distinct 16MB "pages" that
+ * are used by UMA, the physical memory allocator reduces the likelihood of
+ * both 2MB page TLB misses and cache misses during the page table walk when
+ * a 2MB page TLB miss does occur.
  */
-#define	VM_NFREEORDER		12
+#define	VM_NFREEORDER		13
 
 /*
  * Enable superpage reservations: 1 level.