git: 56c202de785a - main - tegra210: change to UTF-8 (from ISO-8859)
Date: Fri, 29 Dec 2023 14:51:12 UTC
The branch main has been updated by emaste: URL: https://cgit.FreeBSD.org/src/commit/?id=56c202de785a5701831ae345a1a5c906e0b2c3e6 commit 56c202de785a5701831ae345a1a5c906e0b2c3e6 Author: Ed Maste <emaste@FreeBSD.org> AuthorDate: 2023-12-29 03:53:16 +0000 Commit: Ed Maste <emaste@FreeBSD.org> CommitDate: 2023-12-29 14:51:00 +0000 tegra210: change to UTF-8 (from ISO-8859) Prompted by Phabricator's complaint that a C source file was a binary file, in D43192. Reviewed by: mmel Differential Revision: https://reviews.freebsd.org/D43229 --- sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c b/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c index e51cf74a3127..c3bf2d54668b 100644 --- a/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c +++ b/sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c @@ -655,7 +655,7 @@ uphy_pex_enable(struct padctl_softc *sc, struct padctl_pad *pad) goto err; } - /* 5. Enable the PLL (20 µs Lock time) */ + /* 5. Enable the PLL (20 μs Lock time) */ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE; WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); @@ -890,7 +890,7 @@ uphy_sata_enable(struct padctl_softc *sc, struct padctl_pad *pad, bool usb) goto err; } - /* 5. Enable the PLL (20 µs Lock time) */ + /* 5. Enable the PLL (20 μs Lock time) */ reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE; WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg);