git: 61e2161367bb - main - x86: Adjust base addr for PCI MCFG regions

From: Colin Percival <cperciva_at_FreeBSD.org>
Date: Wed, 27 Dec 2023 21:15:07 UTC
The branch main has been updated by cperciva:

URL: https://cgit.FreeBSD.org/src/commit/?id=61e2161367bb4e68e603f53b1107f9427f988861

commit 61e2161367bb4e68e603f53b1107f9427f988861
Author:     Colin Percival <cperciva@FreeBSD.org>
AuthorDate: 2023-12-27 08:09:08 +0000
Commit:     Colin Percival <cperciva@FreeBSD.org>
CommitDate: 2023-12-27 21:14:47 +0000

    x86: Adjust base addr for PCI MCFG regions
    
    Each bus gets 1 MB of address space; the actual base address for an
    MCFG bus range is the address from the table plus the starting bus
    number times 1 MB.
    
    The PCI spec is unclear on this point, but this change matches what
    Linux does, which is likely enough of a de facto standard regardless
    of what any de jure standard might attempt to say.
    
    Fixes:  f54a3890b1f4 ("x86: Support multiple PCI MCFG regions")
    Reviewed by:    jhb
    Differential Revision:  https://reviews.freebsd.org/D43206
---
 sys/amd64/pci/pci_cfgreg.c | 2 +-
 sys/i386/pci/pci_cfgreg.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c
index 21e8d9c21228..90e15b15553d 100644
--- a/sys/amd64/pci/pci_cfgreg.c
+++ b/sys/amd64/pci/pci_cfgreg.c
@@ -296,7 +296,7 @@ pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus)
 	region = &mcfg_regions[mcfg_numregions];
 
 	/* XXX: We should make sure this really fits into the direct map. */
-	region->base = pmap_mapdev_pciecfg(base, (maxbus + 1 - minbus) << 20);
+	region->base = pmap_mapdev_pciecfg(base + (minbus << 20), (maxbus + 1 - minbus) << 20);
 	region->domain = domain;
 	region->minbus = minbus;
 	region->maxbus = maxbus;
diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c
index b2cd23687ccc..bb6258ccf214 100644
--- a/sys/i386/pci/pci_cfgreg.c
+++ b/sys/i386/pci/pci_cfgreg.c
@@ -574,7 +574,7 @@ pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus)
 	    sizeof(*mcfg_regions) * (mcfg_numregions + 1), M_DEVBUF, M_WAITOK);
 
 	region = &mcfg_regions[mcfg_numregions];
-	region->base = base;
+	region->base = base + (minbus << 20);
 	region->domain = domain;
 	region->minbus = minbus;
 	region->maxbus = maxbus;