git: 22029445cbef - main - eqos: Unbreak fdt support

The branch main has been updated by manu:

URL: https://cgit.FreeBSD.org/src/commit/?id=22029445cbef0ffc71196a6f38cee4738e9a6d0f

commit 22029445cbef0ffc71196a6f38cee4738e9a6d0f
Author:     Emmanuel Vadot <manu@FreeBSD.org>
AuthorDate: 2023-12-11 10:29:16 +0000
Commit:     Emmanuel Vadot <manu@FreeBSD.org>
CommitDate: 2023-12-11 10:31:26 +0000

    eqos: Unbreak fdt support
    
    We need to enable the clocks and deassert the resets for eqos to work
    correctly.
---
 sys/dev/eqos/if_eqos_fdt.c | 56 ++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 54 insertions(+), 2 deletions(-)

diff --git a/sys/dev/eqos/if_eqos_fdt.c b/sys/dev/eqos/if_eqos_fdt.c
index 17241b1c560b..68fcbc1ea706 100644
--- a/sys/dev/eqos/if_eqos_fdt.c
+++ b/sys/dev/eqos/if_eqos_fdt.c
@@ -50,6 +50,7 @@
 #include <dev/ofw/ofw_bus.h>
 #include <dev/ofw/ofw_bus_subr.h>
 
+#include <dev/extres/clk/clk.h>
 #include <dev/extres/hwreset/hwreset.h>
 #include <dev/extres/regulator/regulator.h>
 #include <dev/extres/syscon/syscon.h>
@@ -148,6 +149,9 @@ eqos_fdt_init(device_t dev)
 	regulator_t eqos_supply;
 	uint32_t rx_delay, tx_delay;
 	uint8_t buffer[16];
+	clk_t stmmaceth, mac_clk_rx, mac_clk_tx, aclk_mac, pclk_mac;
+	uint64_t freq;
+	int error;
 
 	if (OF_hasprop(node, "rockchip,grf") &&
 	    syscon_get_by_ofw_property(dev, node, "rockchip,grf", &sc->grf)) {
@@ -174,8 +178,56 @@ eqos_fdt_init(device_t dev)
 		device_printf(dev, "cannot get reset\n");
 		return (ENXIO);
 	}
-	else
-		hwreset_assert(eqos_reset);
+	hwreset_assert(eqos_reset);
+
+	error = clk_set_assigned(dev, ofw_bus_get_node(dev));
+	if (error != 0) {
+		device_printf(dev, "clk_set_assigned failed\n");
+		return (error);
+	}
+
+	if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &stmmaceth) == 0) {
+		error = clk_enable(stmmaceth);
+		if (error != 0) {
+			device_printf(dev, "could not enable main clock\n");
+			return (error);
+		}
+		if (bootverbose) {
+			clk_get_freq(stmmaceth, &freq);
+			device_printf(dev, "MAC clock(%s) freq: %jd\n",
+					clk_get_name(stmmaceth), (intmax_t)freq);
+		}
+	}
+	else {
+		device_printf(dev, "could not find clock stmmaceth\n");
+	}
+
+	if (clk_get_by_ofw_name(dev, 0, "mac_clk_rx", &mac_clk_rx) != 0) {
+		device_printf(dev, "could not get mac_clk_rx clock\n");
+		mac_clk_rx = NULL;
+	}
+
+	if (clk_get_by_ofw_name(dev, 0, "mac_clk_tx", &mac_clk_tx) != 0) {
+		device_printf(dev, "could not get mac_clk_tx clock\n");
+		mac_clk_tx = NULL;
+	}
+
+	if (clk_get_by_ofw_name(dev, 0, "aclk_mac", &aclk_mac) != 0) {
+		device_printf(dev, "could not get aclk_mac clock\n");
+		aclk_mac = NULL;
+	}
+
+	if (clk_get_by_ofw_name(dev, 0, "pclk_mac", &pclk_mac) != 0) {
+		device_printf(dev, "could not get pclk_mac clock\n");
+		pclk_mac = NULL;
+	}
+
+	if (aclk_mac)
+		clk_enable(aclk_mac);
+	if (pclk_mac)
+		clk_enable(pclk_mac);
+	if (mac_clk_tx)
+		clk_enable(mac_clk_tx);
 
 	sc->csr_clock = 125000000;
 	sc->csr_clock_range = GMAC_MAC_MDIO_ADDRESS_CR_100_150;