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Wed, 19 Oct 2022 23:23:44 GMT (envelope-from git) Date: Wed, 19 Oct 2022 23:23:44 GMT Message-Id: <202210192323.29JNNim2021547@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Eric Joyner Subject: git: b04c95489864 - stable/12 - ice(4): Update to 1.34.2-k List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: erj X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: b04c954898643ad87b35dacd2fb74885816d798f Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1666221825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; 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this is useful for debugging - General bug fixes - Adds initial DCB support to the driver - Notably, this adds support for DCBX to the driver; now with the fw_lldp sysctl set to 1, the driver and adapter will adopt a DCBX configuration sent from a link partner - Adds statistcs sysctls for priority flow control frames - Adds new configuration sysctls for DCB-related features: (VLAN) user priority to TC mapping; ETS bandwidth allocation; priority flow control - Remove unused SR-IOV files (until support gets added) (MFC node: This adds support for E82x devices (codename Columbia Park) Signed-off-by: Eric Joyner Tested by: jeffrey.e.pieper@intel.com MFC with: 213e91399b, e438f0a975 Relnotes: yes Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D34024 (cherry picked from commit 56429daea255fa719169bb23ded66f8edb6f5408) (cherry picked from commit 61d83041ab111fe491409f2eca2b528108b9ec29) --- sys/conf/files.amd64 | 6 +- sys/conf/files.arm64 | 8 +- sys/dev/ice/ice_adminq_cmd.h | 175 ++-- sys/dev/ice/ice_common.c | 723 +++++++++++++-- sys/dev/ice/ice_common.h | 47 +- sys/dev/ice/ice_dcb.c | 212 ++++- sys/dev/ice/ice_dcb.h | 21 +- sys/dev/ice/ice_devids.h | 12 + sys/dev/ice/ice_drv_info.h | 25 +- sys/dev/ice/ice_features.h | 2 + sys/dev/ice/ice_flex_pipe.c | 14 +- sys/dev/ice/ice_flex_type.h | 4 +- sys/dev/ice/ice_flow.c | 46 +- sys/dev/ice/ice_flow.h | 9 +- sys/dev/ice/ice_fw_logging.c | 425 +++++++++ sys/dev/ice/ice_fwlog.c | 505 +++++++++++ sys/dev/ice/ice_fwlog.h | 91 ++ sys/dev/ice/ice_hw_autogen.h | 148 ++-- sys/dev/ice/ice_iflib.h | 6 + sys/dev/ice/ice_iflib_txrx.c | 82 +- sys/dev/ice/ice_lan_tx_rx.h | 27 +- sys/dev/ice/ice_lib.c | 1662 ++++++++++++++++++++++++++++++++--- sys/dev/ice/ice_lib.h | 39 +- sys/dev/ice/ice_nvm.c | 69 +- sys/dev/ice/ice_nvm.h | 13 - sys/dev/ice/ice_osdep.c | 36 + sys/dev/ice/ice_osdep.h | 2 + sys/dev/ice/ice_protocol_type.h | 14 +- sys/dev/ice/ice_sched.c | 63 +- sys/dev/ice/ice_sriov.c | 596 ------------- sys/dev/ice/ice_sriov.h | 65 -- sys/dev/ice/ice_strings.c | 130 +++ sys/dev/ice/ice_switch.c | 73 +- sys/dev/ice/ice_switch.h | 12 + sys/dev/ice/ice_type.h | 83 +- sys/dev/ice/ice_vlan_mode.c | 74 +- sys/dev/ice/ice_vlan_mode.h | 2 +- sys/dev/ice/if_ice_iflib.c | 42 +- sys/dev/ice/virtchnl.h | 613 ++++++++++++- sys/dev/ice/virtchnl_inline_ipsec.h | 36 +- sys/dev/ice/virtchnl_lan_desc.h | 293 +++--- sys/modules/ice/Makefile | 3 +- 42 files changed, 5078 insertions(+), 1430 deletions(-) diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64 index a71c228ec9f0..26f8bbdd37d1 100644 --- a/sys/conf/files.amd64 +++ b/sys/conf/files.amd64 @@ -299,12 +299,14 @@ dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" -dev/ice/ice_sriov.c optional ice pci \ - compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_vlan_mode.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" +dev/ice/ice_fw_logging.c optional ice pci \ + compile-with "${NORMAL_C} -I$S/dev/ice" +dev/ice/ice_fwlog.c optional ice pci \ + compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01031b00 -mice_ddp -c${.TARGET}" \ no-ctfconvert no-implicit-rule before-depend local \ diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 130a0737c417..219cdf19b0ca 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -254,11 +254,13 @@ dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" -dev/ice/ice_sriov.c optional ice pci \ +dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" -dev/ice/ice_switch.c optional ice pci \ +dev/ice/ice_vlan_mode.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" -dev/ice/ice_vlan_mode.c optional ice pci \ +dev/ice/ice_fw_logging.c optional ice pci \ + compile-with "${NORMAL_C} -I$S/dev/ice" +dev/ice/ice_fwlog.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01031b00 -mice_ddp -c${.TARGET}" \ diff --git a/sys/dev/ice/ice_adminq_cmd.h b/sys/dev/ice/ice_adminq_cmd.h index 5e8560dccb1e..eae8a412d1cc 100644 --- a/sys/dev/ice/ice_adminq_cmd.h +++ b/sys/dev/ice/ice_adminq_cmd.h @@ -169,6 +169,10 @@ struct ice_aqc_list_caps_elem { #define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076 #define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077 #define ICE_AQC_CAPS_NVM_MGMT 0x0080 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0 0x0081 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083 +#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084 u8 major_ver; u8 minor_ver; @@ -1240,10 +1244,11 @@ struct ice_aqc_get_phy_caps { /* 18.0 - Report qualified modules */ #define ICE_AQC_GET_PHY_RQM BIT(0) /* 18.1 - 18.3 : Report mode - * 000b - Report NVM capabilities - * 001b - Report topology capabilities - * 010b - Report SW configured - * 100b - Report default capabilities + * 000b - Report topology capabilities, without media + * 001b - Report topology capabilities, with media + * 010b - Report Active configuration + * 011b - Report PHY Type and FEC mode capabilities + * 100b - Report Default capabilities */ #define ICE_AQC_REPORT_MODE_S 1 #define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S) @@ -1586,6 +1591,7 @@ struct ice_aqc_set_event_mask { #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9) #define ICE_AQ_LINK_EVENT_TOPO_CONFLICT BIT(10) #define ICE_AQ_LINK_EVENT_MEDIA_CONFLICT BIT(11) +#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12) u8 reserved1[6]; }; @@ -1774,7 +1780,7 @@ struct ice_aqc_dnl_read_log_response { }; -struct ice_aqc_link_topo_addr { +struct ice_aqc_link_topo_params { u8 lport_num; u8 lport_num_valid; #define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0) @@ -1800,6 +1806,10 @@ struct ice_aqc_link_topo_addr { #define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4 #define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5 u8 index; +}; + +struct ice_aqc_link_topo_addr { + struct ice_aqc_link_topo_params topo_params; __le16 handle; #define ICE_AQC_LINK_TOPO_HANDLE_S 0 #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) @@ -1822,59 +1832,10 @@ struct ice_aqc_link_topo_addr { struct ice_aqc_get_link_topo { struct ice_aqc_link_topo_addr addr; u8 node_part_num; +#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 u8 rsvd[9]; }; -/* Get Link Topology Pin (direct, 0x06E1) */ -struct ice_aqc_get_link_topo_pin { - struct ice_aqc_link_topo_addr addr; - u8 input_io_params; -#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S 0 -#define ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_M \ - (0x1F << ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_S) -#define ICE_AQC_LINK_TOPO_IO_FUNC_GPIO 0 -#define ICE_AQC_LINK_TOPO_IO_FUNC_RESET_N 1 -#define ICE_AQC_LINK_TOPO_IO_FUNC_INT_N 2 -#define ICE_AQC_LINK_TOPO_IO_FUNC_PRESENT_N 3 -#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_DIS 4 -#define ICE_AQC_LINK_TOPO_IO_FUNC_MODSEL_N 5 -#define ICE_AQC_LINK_TOPO_IO_FUNC_LPMODE 6 -#define ICE_AQC_LINK_TOPO_IO_FUNC_TX_FAULT 7 -#define ICE_AQC_LINK_TOPO_IO_FUNC_RX_LOSS 8 -#define ICE_AQC_LINK_TOPO_IO_FUNC_RS0 9 -#define ICE_AQC_LINK_TOPO_IO_FUNC_RS1 10 -#define ICE_AQC_LINK_TOPO_IO_FUNC_EEPROM_WP 11 -/* 12 repeats intentionally due to two different uses depending on context */ -#define ICE_AQC_LINK_TOPO_IO_FUNC_LED 12 -#define ICE_AQC_LINK_TOPO_IO_FUNC_RED_LED 12 -#define ICE_AQC_LINK_TOPO_IO_FUNC_GREEN_LED 13 -#define ICE_AQC_LINK_TOPO_IO_FUNC_BLUE_LED 14 -#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S 5 -#define ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_M \ - (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) -/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ - u8 output_io_params; -#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_S 0 -#define ICE_AQC_LINK_TOPO_OUTPUT_IO_FUNC_M \ - (0x1F << \ ICE_AQC_LINK_TOPO_INPUT_IO_FUNC_NUM_S) -/* Use ICE_AQC_LINK_TOPO_IO_FUNC_* for the non-numerical options */ -#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_S 5 -#define ICE_AQC_LINK_TOPO_OUTPUT_IO_TYPE_M \ - (0x7 << ICE_AQC_LINK_TOPO_INPUT_IO_TYPE_S) -/* Use ICE_AQC_LINK_TOPO_NODE_TYPE_* for the type values */ - u8 output_io_flags; -#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S 0 -#define ICE_AQC_LINK_TOPO_OUTPUT_SPEED_M \ - (0x7 << ICE_AQC_LINK_TOPO_OUTPUT_SPEED_S) -#define ICE_AQC_LINK_TOPO_OUTPUT_INT_S 3 -#define ICE_AQC_LINK_TOPO_OUTPUT_INT_M \ - (0x3 << ICE_AQC_LINK_TOPO_OUTPUT_INT_S) -#define ICE_AQC_LINK_TOPO_OUTPUT_POLARITY BIT(5) -#define ICE_AQC_LINK_TOPO_OUTPUT_VALUE BIT(6) -#define ICE_AQC_LINK_TOPO_OUTPUT_DRIVEN BIT(7) - u8 rsvd[7]; -}; - /* Read/Write I2C (direct, 0x06E2/0x06E3) */ struct ice_aqc_i2c { struct ice_aqc_link_topo_addr topo_addr; @@ -2072,23 +2033,18 @@ struct ice_aqc_sw_gpio { u8 rsvd[12]; }; -/* Program topology device NVM (direct, 0x06F2) */ -struct ice_aqc_program_topology_device_nvm { - u8 lport_num; - u8 lport_num_valid; - u8 node_type_ctx; - u8 index; +/* Program Topology Device NVM (direct, 0x06F2) */ +struct ice_aqc_prog_topo_dev_nvm { + struct ice_aqc_link_topo_params topo_params; u8 rsvd[12]; }; -/* Read topology device NVM (indirect, 0x06F3) */ -struct ice_aqc_read_topology_device_nvm { - u8 lport_num; - u8 lport_num_valid; - u8 node_type_ctx; - u8 index; +/* Read Topology Device NVM (direct, 0x06F3) */ +struct ice_aqc_read_topo_dev_nvm { + struct ice_aqc_link_topo_params topo_params; __le32 start_address; - u8 data_read[8]; +#define ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8 + u8 data_read[ICE_AQC_READ_TOPO_DEV_NVM_DATA_READ_SIZE]; }; /* NVM Read command (indirect 0x0701) @@ -2117,10 +2073,11 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */ #define ICE_AQC_NVM_ACTIV_SEL_MASK MAKEMASK(0x7, 3) #define ICE_AQC_NVM_FLASH_ONLY BIT(7) -#define ICE_AQC_NVM_POR_FLAG 0 /* Used by NVM Write completion on ARQ */ -#define ICE_AQC_NVM_PERST_FLAG 1 -#define ICE_AQC_NVM_EMPR_FLAG 2 -#define ICE_AQC_NVM_EMPR_ENA BIT(0) +#define ICE_AQC_NVM_RESET_LVL_M MAKEMASK(0x3, 0) /* Write reply only */ +#define ICE_AQC_NVM_POR_FLAG 0 +#define ICE_AQC_NVM_PERST_FLAG 1 +#define ICE_AQC_NVM_EMPR_FLAG 2 +#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */ __le16 module_typeid; __le16 length; #define ICE_AQC_NVM_ERASE_LEN 0xFFFF @@ -2665,6 +2622,63 @@ struct ice_aqc_event_lan_overflow { u8 reserved[8]; }; +/* Debug Dump Internal Data (indirect 0xFF08) */ +struct ice_aqc_debug_dump_internals { + u8 cluster_id; +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 +/* EMP_DRAM only dumpable in device debug mode */ +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 +/* AUX_REGS only dumpable in device debug mode */ +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 + u8 reserved; + __le16 table_id; /* Used only for non-memory clusters */ + __le32 idx; /* In table entries for tables, in bytes for memory */ + __le32 addr_high; + __le32 addr_low; +}; + +enum ice_aqc_fw_logging_mod { + ICE_AQC_FW_LOG_ID_GENERAL = 0, + ICE_AQC_FW_LOG_ID_CTRL, + ICE_AQC_FW_LOG_ID_LINK, + ICE_AQC_FW_LOG_ID_LINK_TOPO, + ICE_AQC_FW_LOG_ID_DNL, + ICE_AQC_FW_LOG_ID_I2C, + ICE_AQC_FW_LOG_ID_SDP, + ICE_AQC_FW_LOG_ID_MDIO, + ICE_AQC_FW_LOG_ID_ADMINQ, + ICE_AQC_FW_LOG_ID_HDMA, + ICE_AQC_FW_LOG_ID_LLDP, + ICE_AQC_FW_LOG_ID_DCBX, + ICE_AQC_FW_LOG_ID_DCB, + ICE_AQC_FW_LOG_ID_XLR, + ICE_AQC_FW_LOG_ID_NVM, + ICE_AQC_FW_LOG_ID_AUTH, + ICE_AQC_FW_LOG_ID_VPD, + ICE_AQC_FW_LOG_ID_IOSF, + ICE_AQC_FW_LOG_ID_PARSER, + ICE_AQC_FW_LOG_ID_SW, + ICE_AQC_FW_LOG_ID_SCHEDULER, + ICE_AQC_FW_LOG_ID_TXQ, + ICE_AQC_FW_LOG_ID_RSVD, + ICE_AQC_FW_LOG_ID_POST, + ICE_AQC_FW_LOG_ID_WATCHDOG, + ICE_AQC_FW_LOG_ID_TASK_DISPATCH, + ICE_AQC_FW_LOG_ID_MNG, + ICE_AQC_FW_LOG_ID_SYNCE, + ICE_AQC_FW_LOG_ID_HEALTH, + ICE_AQC_FW_LOG_ID_TSDRV, + ICE_AQC_FW_LOG_ID_PFREG, + ICE_AQC_FW_LOG_ID_MDLVER, + ICE_AQC_FW_LOG_ID_MAX, +}; + + /* Set Health Status (direct 0xFF20) */ struct ice_aqc_set_health_status_config { u8 event_source; @@ -2694,6 +2708,8 @@ struct ice_aqc_set_health_status_config { #define ICE_AQC_HEALTH_STATUS_ERR_LINK_HW_ACCESS 0x115 #define ICE_AQC_HEALTH_STATUS_ERR_LINK_RUNTIME 0x116 #define ICE_AQC_HEALTH_STATUS_ERR_DNL_INIT 0x117 +#define ICE_AQC_HEALTH_STATUS_ERR_PHY_NVM_PROG 0x120 +#define ICE_AQC_HEALTH_STATUS_ERR_PHY_FW_LOAD 0x121 #define ICE_AQC_HEALTH_STATUS_INFO_RECOVERY 0x500 #define ICE_AQC_HEALTH_STATUS_ERR_FLASH_ACCESS 0x501 #define ICE_AQC_HEALTH_STATUS_ERR_NVM_AUTH 0x502 @@ -2745,11 +2761,11 @@ struct ice_aqc_clear_health_status { * Get FW Log (indirect 0xFF34) * Clear FW Log (indirect 0xFF35) */ - struct ice_aqc_fw_log { u8 cmd_flags; #define ICE_AQC_FW_LOG_CONF_UART_EN BIT(0) #define ICE_AQC_FW_LOG_CONF_AQ_EN BIT(1) +#define ICE_AQC_FW_LOG_QUERY_REGISTERED BIT(2) #define ICE_AQC_FW_LOG_CONF_SET_VALID BIT(3) #define ICE_AQC_FW_LOG_AQ_REGISTER BIT(0) #define ICE_AQC_FW_LOG_AQ_QUERY BIT(2) @@ -2837,6 +2853,7 @@ struct ice_aq_desc { struct ice_aqc_mdio read_write_mdio; struct ice_aqc_gpio_by_func read_write_gpio_by_func; struct ice_aqc_gpio read_write_gpio; + struct ice_aqc_sw_gpio sw_read_write_gpio; struct ice_aqc_set_led set_led; struct ice_aqc_mdio read_mdio; struct ice_aqc_mdio write_mdio; @@ -2887,6 +2904,8 @@ struct ice_aq_desc { struct ice_aqc_download_pkg download_pkg; struct ice_aqc_get_pkg_info_list get_pkg_info_list; struct ice_aqc_driver_shared_params drv_shared_params; + struct ice_aqc_fw_log fw_log; + struct ice_aqc_debug_dump_internals debug_dump; struct ice_aqc_set_mac_lb set_mac_lb; struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; struct ice_aqc_get_res_alloc get_res; @@ -2902,6 +2921,8 @@ struct ice_aq_desc { get_supported_health_status_codes; struct ice_aqc_get_health_status get_health_status; struct ice_aqc_clear_health_status clear_health_status; + struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm; + struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm; } params; }; @@ -3069,7 +3090,6 @@ enum ice_adminq_opc { ice_aqc_opc_dnl_set_breakpoints = 0x0686, ice_aqc_opc_dnl_read_log = 0x0687, ice_aqc_opc_get_link_topo = 0x06E0, - ice_aqc_opc_get_link_topo_pin = 0x06E1, ice_aqc_opc_read_i2c = 0x06E2, ice_aqc_opc_write_i2c = 0x06E3, ice_aqc_opc_read_mdio = 0x06E4, @@ -3085,8 +3105,8 @@ enum ice_adminq_opc { ice_aqc_opc_sff_eeprom = 0x06EE, ice_aqc_opc_sw_set_gpio = 0x06EF, ice_aqc_opc_sw_get_gpio = 0x06F0, - ice_aqc_opc_program_topology_device_nvm = 0x06F2, - ice_aqc_opc_read_topology_device_nvm = 0x06F3, + ice_aqc_opc_prog_topo_dev_nvm = 0x06F2, + ice_aqc_opc_read_topo_dev_nvm = 0x06F3, /* NVM commands */ ice_aqc_opc_nvm_read = 0x0701, @@ -3148,6 +3168,9 @@ enum ice_adminq_opc { /* Standalone Commands/Events */ ice_aqc_opc_event_lan_overflow = 0x1001, + /* debug commands */ + ice_aqc_opc_debug_dump_internals = 0xFF08, + /* SystemDiagnostic commands */ ice_aqc_opc_set_health_status_config = 0xFF20, ice_aqc_opc_get_supported_health_status_codes = 0xFF21, diff --git a/sys/dev/ice/ice_common.c b/sys/dev/ice/ice_common.c index 1e5d6dcb7d30..80aa3557bf75 100644 --- a/sys/dev/ice/ice_common.c +++ b/sys/dev/ice/ice_common.c @@ -39,6 +39,120 @@ #define ICE_PF_RESET_WAIT_COUNT 300 +/** + * dump_phy_type - helper function that prints PHY type strings + * @hw: pointer to the HW structure + * @phy: 64 bit PHY type to decipher + * @i: bit index within phy + * @phy_string: string corresponding to bit i in phy + * @prefix: prefix string to differentiate multiple dumps + */ +static void +dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string, + const char *prefix) +{ + if (phy & BIT_ULL(i)) + ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i, + phy_string); +} + +/** + * ice_dump_phy_type_low - helper function to dump phy_type_low + * @hw: pointer to the HW structure + * @low: 64 bit value for phy_type_low + * @prefix: prefix string to differentiate multiple dumps + */ +static void +ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix) +{ + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix, + (unsigned long long)low); + + dump_phy_type(hw, low, 0, "100BASE_TX", prefix); + dump_phy_type(hw, low, 1, "100M_SGMII", prefix); + dump_phy_type(hw, low, 2, "1000BASE_T", prefix); + dump_phy_type(hw, low, 3, "1000BASE_SX", prefix); + dump_phy_type(hw, low, 4, "1000BASE_LX", prefix); + dump_phy_type(hw, low, 5, "1000BASE_KX", prefix); + dump_phy_type(hw, low, 6, "1G_SGMII", prefix); + dump_phy_type(hw, low, 7, "2500BASE_T", prefix); + dump_phy_type(hw, low, 8, "2500BASE_X", prefix); + dump_phy_type(hw, low, 9, "2500BASE_KX", prefix); + dump_phy_type(hw, low, 10, "5GBASE_T", prefix); + dump_phy_type(hw, low, 11, "5GBASE_KR", prefix); + dump_phy_type(hw, low, 12, "10GBASE_T", prefix); + dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix); + dump_phy_type(hw, low, 14, "10GBASE_SR", prefix); + dump_phy_type(hw, low, 15, "10GBASE_LR", prefix); + dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix); + dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix); + dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix); + dump_phy_type(hw, low, 19, "25GBASE_T", prefix); + dump_phy_type(hw, low, 20, "25GBASE_CR", prefix); + dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix); + dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix); + dump_phy_type(hw, low, 23, "25GBASE_SR", prefix); + dump_phy_type(hw, low, 24, "25GBASE_LR", prefix); + dump_phy_type(hw, low, 25, "25GBASE_KR", prefix); + dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix); + dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix); + dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix); + dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix); + dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix); + dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix); + dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix); + dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix); + dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix); + dump_phy_type(hw, low, 35, "40G_XLAUI", prefix); + dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix); + dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix); + dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix); + dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix); + dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix); + dump_phy_type(hw, low, 41, "50G_LAUI2", prefix); + dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix); + dump_phy_type(hw, low, 43, "50G_AUI2", prefix); + dump_phy_type(hw, low, 44, "50GBASE_CP", prefix); + dump_phy_type(hw, low, 45, "50GBASE_SR", prefix); + dump_phy_type(hw, low, 46, "50GBASE_FR", prefix); + dump_phy_type(hw, low, 47, "50GBASE_LR", prefix); + dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix); + dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix); + dump_phy_type(hw, low, 50, "50G_AUI1", prefix); + dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix); + dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix); + dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix); + dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix); + dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix); + dump_phy_type(hw, low, 56, "100G_CAUI4", prefix); + dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix); + dump_phy_type(hw, low, 58, "100G_AUI4", prefix); + dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix); + dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix); + dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix); + dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix); + dump_phy_type(hw, low, 63, "100GBASE_DR", prefix); +} + +/** + * ice_dump_phy_type_high - helper function to dump phy_type_high + * @hw: pointer to the HW structure + * @high: 64 bit value for phy_type_high + * @prefix: prefix string to differentiate multiple dumps + */ +static void +ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix) +{ + ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix, + (unsigned long long)high); + + dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix); + dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix); + dump_phy_type(hw, high, 2, "100G_CAUI2", prefix); + dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix); + dump_phy_type(hw, high, 4, "100G_AUI2", prefix); +} + /** * ice_set_mac_type - Sets MAC type * @hw: pointer to the HW structure @@ -76,6 +190,11 @@ enum ice_status ice_set_mac_type(struct ice_hw *hw) case ICE_DEV_ID_E823L_BACKPLANE: case ICE_DEV_ID_E823L_QSFP: case ICE_DEV_ID_E823L_SFP: + case ICE_DEV_ID_E823C_10G_BASE_T: + case ICE_DEV_ID_E823C_BACKPLANE: + case ICE_DEV_ID_E823C_QSFP: + case ICE_DEV_ID_E823C_SFP: + case ICE_DEV_ID_E823C_SGMII: hw->mac_type = ICE_MAC_GENERIC; break; default: @@ -87,6 +206,42 @@ enum ice_status ice_set_mac_type(struct ice_hw *hw) return ICE_SUCCESS; } +/** + * ice_is_e810 + * @hw: pointer to the hardware structure + * + * returns true if the device is E810 based, false if not. + */ +bool ice_is_e810(struct ice_hw *hw) +{ + return hw->mac_type == ICE_MAC_E810; +} + +/** + * ice_is_e810t + * @hw: pointer to the hardware structure + * + * returns true if the device is E810T based, false if not. + */ +bool ice_is_e810t(struct ice_hw *hw) +{ + switch (hw->device_id) { + case ICE_DEV_ID_E810C_SFP: + if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T || + hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) + return true; + break; + case ICE_DEV_ID_E810C_QSFP: + if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2) + return true; + break; + default: + break; + } + + return false; +} + /** * ice_clear_pf_cfg - Clear PF configuration * @hw: pointer to the hardware structure @@ -181,6 +336,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, u16 pcaps_size = sizeof(*pcaps); struct ice_aq_desc desc; enum ice_status status; + const char *prefix; struct ice_hw *hw; cmd = &desc.params.get_phy; @@ -201,29 +357,42 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, cmd->param0 |= CPU_TO_LE16(report_mode); status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd); - ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n", - report_mode); - ice_debug(hw, ICE_DBG_LINK, " phy_type_low = 0x%llx\n", - (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low)); - ice_debug(hw, ICE_DBG_LINK, " phy_type_high = 0x%llx\n", - (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high)); - ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", pcaps->caps); - ice_debug(hw, ICE_DBG_LINK, " low_power_ctrl_an = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n"); + + if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) + prefix = "phy_caps_media"; + else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA) + prefix = "phy_caps_no_media"; + else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG) + prefix = "phy_caps_active"; + else if (report_mode == ICE_AQC_REPORT_DFLT_CFG) + prefix = "phy_caps_default"; + else + prefix = "phy_caps_invalid"; + + ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix); + ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix); + + ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n", + prefix, report_mode); + ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); + ice_debug(hw, ICE_DBG_LINK, "%s: low_power_ctrl_an = 0x%x\n", prefix, pcaps->low_power_ctrl_an); - ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", pcaps->eee_cap); - ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: eee_cap = 0x%x\n", prefix, + pcaps->eee_cap); + ice_debug(hw, ICE_DBG_LINK, "%s: eeer_value = 0x%x\n", prefix, pcaps->eeer_value); - ice_debug(hw, ICE_DBG_LINK, " link_fec_options = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: link_fec_options = 0x%x\n", prefix, pcaps->link_fec_options); - ice_debug(hw, ICE_DBG_LINK, " module_compliance_enforcement = 0x%x\n", - pcaps->module_compliance_enforcement); - ice_debug(hw, ICE_DBG_LINK, " extended_compliance_code = 0x%x\n", - pcaps->extended_compliance_code); - ice_debug(hw, ICE_DBG_LINK, " module_type[0] = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: module_compliance_enforcement = 0x%x\n", + prefix, pcaps->module_compliance_enforcement); + ice_debug(hw, ICE_DBG_LINK, "%s: extended_compliance_code = 0x%x\n", + prefix, pcaps->extended_compliance_code); + ice_debug(hw, ICE_DBG_LINK, "%s: module_type[0] = 0x%x\n", prefix, pcaps->module_type[0]); - ice_debug(hw, ICE_DBG_LINK, " module_type[1] = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: module_type[1] = 0x%x\n", prefix, pcaps->module_type[1]); - ice_debug(hw, ICE_DBG_LINK, " module_type[2] = 0x%x\n", + ice_debug(hw, ICE_DBG_LINK, "%s: module_type[2] = 0x%x\n", prefix, pcaps->module_type[2]); if (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) { @@ -238,35 +407,76 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode, } /** - * ice_aq_get_link_topo_handle - get link topology node return status - * @pi: port information structure - * @node_type: requested node type - * @cd: pointer to command details structure or NULL - * - * Get link topology node return status for specified node type (0x06E0) - * - * Node type cage can be used to determine if cage is present. If AQC - * returns error (ENOENT), then no cage present. If no cage present, then - * connection type is backplane or BASE-T. + * ice_aq_get_netlist_node + * @hw: pointer to the hw struct + * @cmd: get_link_topo AQ structure + * @node_part_number: output node part number if node found + * @node_handle: output node handle parameter if node found */ -static enum ice_status -ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, - struct ice_sq_cd *cd) +enum ice_status +ice_aq_get_netlist_node(struct ice_hw *hw, struct ice_aqc_get_link_topo *cmd, + u8 *node_part_number, u16 *node_handle) { - struct ice_aqc_get_link_topo *cmd; struct ice_aq_desc desc; - cmd = &desc.params.get_link_topo; - ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); + desc.params.get_link_topo = *cmd; - cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << - ICE_AQC_LINK_TOPO_NODE_CTX_S); + if (ice_aq_send_cmd(hw, &desc, NULL, 0, NULL)) + return ICE_ERR_NOT_SUPPORTED; - /* set node type */ - cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type); + if (node_handle) + *node_handle = + LE16_TO_CPU(desc.params.get_link_topo.addr.handle); + if (node_part_number) + *node_part_number = desc.params.get_link_topo.node_part_num; - return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); + return ICE_SUCCESS; +} + +#define MAX_NETLIST_SIZE 10 +/** + * ice_find_netlist_node + * @hw: pointer to the hw struct + * @node_type_ctx: type of netlist node to look for + * @node_part_number: node part number to look for + * @node_handle: output parameter if node found - optional + * + * Find and return the node handle for a given node type and part number in the + * netlist. When found ICE_SUCCESS is returned, ICE_ERR_DOES_NOT_EXIST + * otherwise. If @node_handle provided, it would be set to found node handle. + */ +enum ice_status +ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number, + u16 *node_handle) +{ + struct ice_aqc_get_link_topo cmd; + u8 rec_node_part_number; + enum ice_status status; + u16 rec_node_handle; + u8 idx; + + for (idx = 0; idx < MAX_NETLIST_SIZE; idx++) { + memset(&cmd, 0, sizeof(cmd)); + + cmd.addr.topo_params.node_type_ctx = + (node_type_ctx << ICE_AQC_LINK_TOPO_NODE_TYPE_S); + cmd.addr.topo_params.index = idx; + + status = ice_aq_get_netlist_node(hw, &cmd, + &rec_node_part_number, + &rec_node_handle); + if (status) + return status; + + if (rec_node_part_number == node_part_number) { + if (node_handle) + *node_handle = rec_node_handle; + return ICE_SUCCESS; + } + } + + return ICE_ERR_DOES_NOT_EXIST; } /** @@ -278,13 +488,27 @@ ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type, */ static bool ice_is_media_cage_present(struct ice_port_info *pi) { + struct ice_aqc_get_link_topo *cmd; + struct ice_aq_desc desc; + + cmd = &desc.params.get_link_topo; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); + + cmd->addr.topo_params.node_type_ctx = + (ICE_AQC_LINK_TOPO_NODE_CTX_PORT << + ICE_AQC_LINK_TOPO_NODE_CTX_S); + + /* set node type */ + cmd->addr.topo_params.node_type_ctx |= + (ICE_AQC_LINK_TOPO_NODE_TYPE_M & + ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE); + /* Node type cage can be used to determine if cage is present. If AQC * returns error (ENOENT), then no cage present. If no cage present then * connection type is backplane or BASE-T. */ - return !ice_aq_get_link_topo_handle(pi, - ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE, - NULL); + return ice_aq_get_netlist_node(pi->hw, cmd, NULL, NULL); } /** @@ -489,6 +713,7 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse, (unsigned long long)li->phy_type_high); ice_debug(hw, ICE_DBG_LINK, " media_type = 0x%x\n", *hw_media_type); ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); + ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); @@ -526,7 +751,7 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, * LFC. Thus, we will use index = * PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX. * - * Also, because we are opearating on transmit timer and fc + * Also, because we are operating on transmit timer and fc * threshold of LFC, we don't turn on any bit in tx_tmr_priority */ #define IDX_OF_LFC PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX @@ -548,12 +773,14 @@ ice_fill_tx_timer_and_fc_thresh(struct ice_hw *hw, * ice_aq_set_mac_cfg * @hw: pointer to the HW struct * @max_frame_size: Maximum Frame Size to be supported + * @auto_drop: Tell HW to drop packets if TC queue is blocked * @cd: pointer to command details structure or NULL * * Set MAC configuration (0x0603) */ enum ice_status -ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) +ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, bool auto_drop, + struct ice_sq_cd *cd) { struct ice_aqc_set_mac_cfg *cmd; struct ice_aq_desc desc; @@ -567,6 +794,8 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) cmd->max_frame_size = CPU_TO_LE16(max_frame_size); + if (ice_is_fw_auto_drop_supported(hw) && auto_drop) + cmd->drop_opts |= ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS; ice_fill_tx_timer_and_fc_thresh(hw, cmd); return ice_aq_send_cmd(hw, &desc, NULL, 0, cd); @@ -667,7 +896,7 @@ ice_cleanup_fltr_mgmt_single(struct ice_hw *hw, struct ice_switch_info *sw) } /** - * ice_cleanup_all_fltr_mgmt - cleanup filter management list and locks + * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks * @hw: pointer to the HW struct */ static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) @@ -723,6 +952,17 @@ void ice_print_rollback_msg(struct ice_hw *hw) nvm_str, hw->fw_maj_ver, hw->fw_min_ver); } +/** + * ice_set_umac_shared + * @hw: pointer to the hw struct + * + * Set boolean flag to allow unicast MAC sharing + */ +void ice_set_umac_shared(struct ice_hw *hw) +{ + hw->umac_shared = true; +} + /** * ice_init_hw - main hardware initialization routine * @hw: pointer to the hardware structure @@ -754,6 +994,25 @@ enum ice_status ice_init_hw(struct ice_hw *hw) if (status) goto err_unroll_cqinit; + ice_fwlog_set_support_ena(hw); + status = ice_fwlog_set(hw, &hw->fwlog_cfg); + if (status) { + ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging, status %d.\n", + status); + } else { + if (hw->fwlog_cfg.options & ICE_FWLOG_OPTION_REGISTER_ON_INIT) { + status = ice_fwlog_register(hw); + if (status) + ice_debug(hw, ICE_DBG_INIT, "Failed to register for FW logging events, status %d.\n", + status); + } else { + status = ice_fwlog_unregister(hw); + if (status) + ice_debug(hw, ICE_DBG_INIT, "Failed to unregister for FW logging events, status %d.\n", + status); + } + } + status = ice_init_nvm(hw); if (status) goto err_unroll_cqinit; @@ -833,6 +1092,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) goto err_unroll_sched; /* Get MAC information */ + /* A single port can report up to two (LAN and WoL) addresses */ mac_buf = ice_calloc(hw, 2, sizeof(struct ice_aqc_manage_mac_read_resp)); @@ -848,10 +1108,13 @@ enum ice_status ice_init_hw(struct ice_hw *hw) if (status) goto err_unroll_fltr_mgmt_struct; + /* enable jumbo frame support at MAC level */ - status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, NULL); + status = ice_aq_set_mac_cfg(hw, ICE_AQ_SET_MAC_FRAME_SIZE_MAX, false, + NULL); if (status) goto err_unroll_fltr_mgmt_struct; + status = ice_init_hw_tbls(hw); if (status) goto err_unroll_fltr_mgmt_struct; @@ -2132,12 +2395,64 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps, caps->num_wol_proxy_fltr); ice_debug(hw, ICE_DBG_INIT, "%s: wol_proxy_vsi_seid = %d\n", prefix, caps->wol_proxy_vsi_seid); + ice_debug(hw, ICE_DBG_INIT, "%s: apm_wol_support = %d\n", + prefix, caps->apm_wol_support); break; case ICE_AQC_CAPS_MAX_MTU: caps->max_mtu = number; ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n", prefix, caps->max_mtu); break; + case ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE: + caps->pcie_reset_avoidance = (number > 0); + ice_debug(hw, ICE_DBG_INIT, + "%s: pcie_reset_avoidance = %d\n", prefix, + caps->pcie_reset_avoidance); + break; + case ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT: + caps->reset_restrict_support = (number == 1); + ice_debug(hw, ICE_DBG_INIT, + "%s: reset_restrict_support = %d\n", prefix, + caps->reset_restrict_support); + break; + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0: + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1: + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2: + case ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3: + { + u8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0; + + caps->ext_topo_dev_img_ver_high[index] = number; + caps->ext_topo_dev_img_ver_low[index] = logical_id; + caps->ext_topo_dev_img_part_num[index] = + (phys_id & ICE_EXT_TOPO_DEV_IMG_PART_NUM_M) >> + ICE_EXT_TOPO_DEV_IMG_PART_NUM_S; + caps->ext_topo_dev_img_load_en[index] = + (phys_id & ICE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0; + caps->ext_topo_dev_img_prog_en[index] = + (phys_id & ICE_EXT_TOPO_DEV_IMG_PROG_EN) != 0; + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_ver_high[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_ver_high[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_ver_low[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_ver_low[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_part_num[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_part_num[index]); + ice_debug(hw, ICE_DBG_INIT, + "%s: ext_topo_dev_img_load_en[%d] = %d\n", + prefix, index, + caps->ext_topo_dev_img_load_en[index]); *** 8012 LINES SKIPPED ***