From nobody Tue Oct 11 13:01:40 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4MmwsJ34P2z4fgrM; Tue, 11 Oct 2022 13:01:40 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4MmwsJ2TGnz3d6G; Tue, 11 Oct 2022 13:01:40 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1665493300; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=AOiFnqAHpPJXJaU2QRqulbKlHDE+5GJXk5UV0xCiMyo=; b=LXiXrTxWp7t59YpgzMoRbNAZSsiepfubv/ez8WayCTq/6bWu7vUQfPEKiaaTTKYU5l9dj2 bQ5skhq1z2036CqTcEhyQchoid11aYdPvtcVoYUTpdD+bcfd6nj+UIcglxpp2To6WTmYlQ g1P0xa8SE/772moX2m9LLMuWYiHksGQvHkhFiQxHNbF2n5dpM1rtcXOin5FkjKlSG9k+5I HnCCjltgngPPP/YLGcaCer4mMb/fl6SAtvxpDHMBcLzNwIjGoS16CuViTtL02dlCbUeAfs HzkwPSh3vu5OyBtIhHpi2e4y8HSduqLv1uw4FlXN4D9p8PKV3nSxayv+KEcEng== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4MmwsJ1X0tzyHf; Tue, 11 Oct 2022 13:01:40 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 29BD1em1036022; Tue, 11 Oct 2022 13:01:40 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 29BD1e38036021; Tue, 11 Oct 2022 13:01:40 GMT (envelope-from git) Date: Tue, 11 Oct 2022 13:01:40 GMT Message-Id: <202210111301.29BD1e38036021@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 12c1c65d8a66 - main - Mark 64-bit arm64 hypervisor registers with UL List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 12c1c65d8a66e7fdd2b99a1bb03cdcf95df0a336 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1665493300; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=AOiFnqAHpPJXJaU2QRqulbKlHDE+5GJXk5UV0xCiMyo=; b=rSgEKJb4A/Tk42o70teMx4G/v5OQ28JZVxuzfrGnjzhuO7eGSSHM05G5qtc9jJm5jwOD2Q TSqJ001Vwbr2hpkJuHRqJY2WRId4fo9SPmzZz7KgwjycELDC2Ay6baDYljDx7kwJ3t73Yq xP4wVktvxWAsxNlS+uHxDFin467SO3T3vwiWYJvPuc8lgK+LsrFnqCy7i3yeLsmczgbgJd QUAMvQRugtDksuJkME4+YbptH5bySw/L6gX1q3Vf2etZ5mcJyuHoZFnJfXPDZi1k4XXDJ0 V965W/HRTrv4avb9QGv9m8keYpGOt5JyDkOoB3BA0Bn7ZrRqhSV8YryEV7ii9w== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1665493300; a=rsa-sha256; cv=none; b=ZljJdA584d4ztn4dJg8PC5Q1TZTa4DvPANvzxMEc515UFnSZYM7RosxaxNWCUgsGDKVx/c A/Fm6M4SSkHNKq/9WebAZF1dTnRdTZFdYEJSVzF7eT2qtIuv2OHZRx5Nu7ftcuHJ2rQq/7 qRORzBeG0JlYfdqgXUQmN5aiMfaJ0AElS2L0VdZZS/5FAmVFBUHs5krl/ycNvnL/7O21U/ tLQLNpG0FfnYzkEA5XvzShpQ+2BKggkak2yC1UPhceR7CB+b6s3X0EDK2NLR7kv8RU9nYE /jWXBdRttp5ADxRxAIt9LnZq6u84opeRxk8n1BMsas2hgZcx/86bX9JchEvYsQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=12c1c65d8a66e7fdd2b99a1bb03cdcf95df0a336 commit 12c1c65d8a66e7fdd2b99a1bb03cdcf95df0a336 Author: Andrew Turner AuthorDate: 2022-09-28 13:39:45 +0000 Commit: Andrew Turner CommitDate: 2022-10-11 13:01:16 +0000 Mark 64-bit arm64 hypervisor registers with UL These are 64-bit. Mark them as unsigned long so we don't rely on undefined behaviour or shift a 32-bit value more than 32 bits. Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation --- sys/arm64/include/hypervisor.h | 78 +++++++++++++++++++++--------------------- 1 file changed, 39 insertions(+), 39 deletions(-) diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h index e8599cb30f3f..f209ecde120a 100644 --- a/sys/arm64/include/hypervisor.h +++ b/sys/arm64/include/hypervisor.h @@ -121,48 +121,48 @@ #define HPFAR_EL2_FIPA_MASK 0xfffffffff0 /* ICC_SRE_EL2 */ -#define ICC_SRE_EL2_SRE (1U << 0) -#define ICC_SRE_EL2_EN (1U << 3) +#define ICC_SRE_EL2_SRE (1UL << 0) +#define ICC_SRE_EL2_EN (1UL << 3) /* SCTLR_EL2 - System Control Register */ #define SCTLR_EL2_RES1 0x30c50830 #define SCTLR_EL2_M_SHIFT 0 -#define SCTLR_EL2_M (0x1 << SCTLR_EL2_M_SHIFT) +#define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT) #define SCTLR_EL2_A_SHIFT 1 -#define SCTLR_EL2_A (0x1 << SCTLR_EL2_A_SHIFT) +#define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT) #define SCTLR_EL2_C_SHIFT 2 -#define SCTLR_EL2_C (0x1 << SCTLR_EL2_C_SHIFT) +#define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT) #define SCTLR_EL2_SA_SHIFT 3 -#define SCTLR_EL2_SA (0x1 << SCTLR_EL2_SA_SHIFT) +#define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT) #define SCTLR_EL2_I_SHIFT 12 -#define SCTLR_EL2_I (0x1 << SCTLR_EL2_I_SHIFT) +#define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT) #define SCTLR_EL2_WXN_SHIFT 19 -#define SCTLR_EL2_WXN (0x1 << SCTLR_EL2_WXN_SHIFT) +#define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT) #define SCTLR_EL2_EE_SHIFT 25 -#define SCTLR_EL2_EE (0x1 << SCTLR_EL2_EE_SHIFT) +#define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT) /* TCR_EL2 - Translation Control Register */ #define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23)) #define TCR_EL2_T0SZ_SHIFT 0 -#define TCR_EL2_T0SZ_MASK (0x3f << TCR_EL2_T0SZ_SHIFT) +#define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT) #define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT) /* Bits 7:6 are reserved */ #define TCR_EL2_IRGN0_SHIFT 8 -#define TCR_EL2_IRGN0_MASK (0x3 << TCR_EL2_IRGN0_SHIFT) +#define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT) #define TCR_EL2_ORGN0_SHIFT 10 -#define TCR_EL2_ORGN0_MASK (0x3 << TCR_EL2_ORGN0_SHIFT) +#define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT) #define TCR_EL2_SH0_SHIFT 12 -#define TCR_EL2_SH0_MASK (0x3 << TCR_EL2_SH0_SHIFT) +#define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT) #define TCR_EL2_TG0_SHIFT 14 -#define TCR_EL2_TG0_MASK (0x3 << TCR_EL2_TG0_SHIFT) +#define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT) #define TCR_EL2_PS_SHIFT 16 -#define TCR_EL2_PS_32BITS (0 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_36BITS (1 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_40BITS (2 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_42BITS (3 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_44BITS (4 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_48BITS (5 << TCR_EL2_PS_SHIFT) -#define TCR_EL2_PS_52BITS (6 << TCR_EL2_PS_SHIFT) /* ARMv8.2-LPA */ +#define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT) +#define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT) +#define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT) +#define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT) +#define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT) +#define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT) +#define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT) /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */ #define VMPIDR_EL2_U 0x0000000040000000 @@ -170,31 +170,31 @@ #define VMPIDR_EL2_RES1 0x0000000080000000 /* VTCR_EL2 - Virtualization Translation Control Register */ -#define VTCR_EL2_RES1 (0x1 << 31) +#define VTCR_EL2_RES1 (0x1UL << 31) #define VTCR_EL2_T0SZ_MASK 0x3f #define VTCR_EL2_SL0_SHIFT 6 -#define VTCR_EL2_SL0_4K_LVL2 (0x0 << VTCR_EL2_SL0_SHIFT) -#define VTCR_EL2_SL0_4K_LVL1 (0x1 << VTCR_EL2_SL0_SHIFT) -#define VTCR_EL2_SL0_4K_LVL0 (0x2 << VTCR_EL2_SL0_SHIFT) +#define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT) +#define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT) +#define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT) #define VTCR_EL2_IRGN0_SHIFT 8 -#define VTCR_EL2_IRGN0_WBWA (0x1 << VTCR_EL2_IRGN0_SHIFT) +#define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT) #define VTCR_EL2_ORGN0_SHIFT 10 -#define VTCR_EL2_ORGN0_WBWA (0x1 << VTCR_EL2_ORGN0_SHIFT) +#define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT) #define VTCR_EL2_SH0_SHIFT 12 -#define VTCR_EL2_SH0_NS (0x0 << VTCR_EL2_SH0_SHIFT) -#define VTCR_EL2_SH0_OS (0x2 << VTCR_EL2_SH0_SHIFT) -#define VTCR_EL2_SH0_IS (0x3 << VTCR_EL2_SH0_SHIFT) +#define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT) +#define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT) +#define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT) #define VTCR_EL2_TG0_SHIFT 14 -#define VTCR_EL2_TG0_4K (0x0 << VTCR_EL2_TG0_SHIFT) -#define VTCR_EL2_TG0_64K (0x1 << VTCR_EL2_TG0_SHIFT) -#define VTCR_EL2_TG0_16K (0x2 << VTCR_EL2_TG0_SHIFT) +#define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT) +#define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT) +#define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT) #define VTCR_EL2_PS_SHIFT 16 -#define VTCR_EL2_PS_32BIT (0x0 << VTCR_EL2_PS_SHIFT) -#define VTCR_EL2_PS_36BIT (0x1 << VTCR_EL2_PS_SHIFT) -#define VTCR_EL2_PS_40BIT (0x2 << VTCR_EL2_PS_SHIFT) -#define VTCR_EL2_PS_42BIT (0x3 << VTCR_EL2_PS_SHIFT) -#define VTCR_EL2_PS_44BIT (0x4 << VTCR_EL2_PS_SHIFT) -#define VTCR_EL2_PS_48BIT (0x5 << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT) +#define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT) /* VTTBR_EL2 - Virtualization Translation Table Base Register */ #define VTTBR_VMID_MASK 0xffff000000000000