From nobody Mon Jul 04 18:09:22 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id A31F41C3F04D; Mon, 4 Jul 2022 18:09:24 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4LcDN30STVz4kKF; Mon, 4 Jul 2022 18:09:23 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1656958163; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=c3TiNe/QHJyh2UVuyG5vKBn/7Za41cgG0m/dAeLDjtE=; b=pCbuVP1tUWHkiwy7eA97YSdvNs2G9dAE4Ibxo8A6nPHryXh8uGJpMtvNWAxZaXiDVsInk2 V6KliP18jiG4TDvf5o3cqU7BqCr+HuY3Q3/jHXwJZntt9GjZ9EKN5Mrg9wr1kc0Fg1zhoC eNXDbX5x6TJKgLqZHs3BEW3xzxnQLvm+XfWhNcN8VdfiW34NF56r+Ol5XRZhbOwrKL8fND iGQZJQBVHyy4wGtL/yI4PrqizsNELMvMNZvHluUYsfRn3f25CLEsmwUfPBvSCuWVLmYBXX hLy86G8R4G1wttXeRKMAk6QJ4VlaffPxgQcHHFo4TcSC1dlzLfZGrj6c9cDxVQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D632715DEA; Mon, 4 Jul 2022 18:09:22 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 264I9MBG064403; Mon, 4 Jul 2022 18:09:22 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 264I9MKe064402; Mon, 4 Jul 2022 18:09:22 GMT (envelope-from git) Date: Mon, 4 Jul 2022 18:09:22 GMT Message-Id: <202207041809.264I9MKe064402@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Alexander Motin Subject: git: b8ef2ca9eae9 - stable/13 - hwpmc: Add basic Intel Alderlake CPUs support. List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mav X-Git-Repository: src X-Git-Refname: refs/heads/stable/13 X-Git-Reftype: branch X-Git-Commit: b8ef2ca9eae9fe8167708413f142d02aa0f02255 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1656958163; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=c3TiNe/QHJyh2UVuyG5vKBn/7Za41cgG0m/dAeLDjtE=; b=K7DP2bBPxJO20BzTljJ/VmmP4MQ1m+5llbYiUyP9XH3TxCg2UArJxHGZLX0BOwy93b14e/ qsGndO+jHJHKeEN9RWmbb35SThh49MJEQcZ3i7RkpCVWrBRHJDlJz/xV5iI37SC5FHh/Uo aSKXyW0hjNS04UlCGduIafue9mQNzmqxBYLNwlRBS4JPRBUPjvVUrC4CT72trY9TrfFfHf tp/EFLrTO2U4nq2YLbFWwmtHxooHqroh6Q7/EalJUNc7ZOWo7Ycbdm9p/GCCgwJT71ofv+ C74K0njlRcTsZy3KjDwn7WRaOCk5NPlj6QrZ/eQmwazC13T8csIbTuKmFjVIRw== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1656958163; a=rsa-sha256; cv=none; b=KO++gvyFZMezx5kqFgcvfxuF9kBAgzZUffkHwjUb1E+5qO0qX9YwbvQ6lk17ycUYOklqJw QU9nu1PLfTMUyJvmma/3HIrf7zNAfy7adytKBjdIouljC+uIzL32SHV9osOqXrKi/hbNFZ kI3z9v9uwF0J19uXW7liOmfZjTO1Thrakox6mgckIwZaVYqT10v85sNHrWxCPhdyMhXj8G q4qOpg4hhLmqsNjdM9OBJBK6LZ6a7fQy0yoeOGcAhLf/pR3QdHgVgJrmLy9rrnIdq2ef/s HOT46DMLZcEOg1rclAVTUpg9hBHmf1jSCvLvZ4beGvKD6vsHlnzzuG/QSCSTIw== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch stable/13 has been updated by mav: URL: https://cgit.FreeBSD.org/src/commit/?id=b8ef2ca9eae9fe8167708413f142d02aa0f02255 commit b8ef2ca9eae9fe8167708413f142d02aa0f02255 Author: Alexander Motin AuthorDate: 2022-05-31 03:17:37 +0000 Commit: Alexander Motin CommitDate: 2022-07-04 17:48:09 +0000 hwpmc: Add basic Intel Alderlake CPUs support. The PMC subsystem is not designed for non-uniform CPU capabilities (P/E-cores are different), but at least several working architectural events like cpu_clk_unhalted.thread_p should be better than nothing. MFC after: 1 month (cherry picked from commit fe109d3113166c8e3b8557f0569c4e5a3597ac93) --- sys/dev/hwpmc/hwpmc_core.c | 1 + sys/dev/hwpmc/hwpmc_intel.c | 107 +++++++++++--------------------------------- sys/sys/pmc.h | 1 + 3 files changed, 29 insertions(+), 80 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c index 2ec6ac794f62..41896ffb7b8e 100644 --- a/sys/dev/hwpmc/hwpmc_core.c +++ b/sys/dev/hwpmc/hwpmc_core.c @@ -785,6 +785,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, case PMC_CPU_INTEL_SKYLAKE_XEON: case PMC_CPU_INTEL_ICELAKE: case PMC_CPU_INTEL_ICELAKE_XEON: + case PMC_CPU_INTEL_ALDERLAKE: default: break; } diff --git a/sys/dev/hwpmc/hwpmc_intel.c b/sys/dev/hwpmc/hwpmc_intel.c index 2d8377e1a838..f59b7b41ece9 100644 --- a/sys/dev/hwpmc/hwpmc_intel.c +++ b/sys/dev/hwpmc/hwpmc_intel.c @@ -163,6 +163,27 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; + case 0x3D: + case 0x47: + cputype = PMC_CPU_INTEL_BROADWELL; + nclasses = 3; + break; + case 0x4f: + case 0x56: + cputype = PMC_CPU_INTEL_BROADWELL_XEON; + nclasses = 3; + break; + case 0x3C: /* Per Intel document 325462-045US 01/2013. */ + case 0x45: /* Per Intel document 325462-045US 09/2014. */ + cputype = PMC_CPU_INTEL_HASWELL; + nclasses = 3; + break; + case 0x3F: /* Per Intel document 325462-045US 09/2014. */ + case 0x46: /* Per Intel document 325462-045US 09/2014. */ + /* Should 46 be XEON. probably its own? */ + cputype = PMC_CPU_INTEL_HASWELL_XEON; + nclasses = 3; + break; /* Skylake */ case 0x4e: case 0x5e: @@ -195,25 +216,9 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_ICELAKE_XEON; nclasses = 3; break; - case 0x3D: - case 0x47: - cputype = PMC_CPU_INTEL_BROADWELL; - nclasses = 3; - break; - case 0x4f: - case 0x56: - cputype = PMC_CPU_INTEL_BROADWELL_XEON; - nclasses = 3; - break; - case 0x3F: /* Per Intel document 325462-045US 09/2014. */ - case 0x46: /* Per Intel document 325462-045US 09/2014. */ - /* Should 46 be XEON. probably its own? */ - cputype = PMC_CPU_INTEL_HASWELL_XEON; - nclasses = 3; - break; - case 0x3C: /* Per Intel document 325462-045US 01/2013. */ - case 0x45: /* Per Intel document 325462-045US 09/2014. */ - cputype = PMC_CPU_INTEL_HASWELL; + case 0x97: + case 0x9A: + cputype = PMC_CPU_INTEL_ALDERLAKE; nclasses = 3; break; case 0x37: @@ -250,40 +255,9 @@ pmc_intel_initialize(void) error = pmc_tsc_initialize(pmc_mdep, ncpus); if (error) goto error; - switch (cputype) { - /* - * Intel Core, Core 2 and Atom processors. - */ - case PMC_CPU_INTEL_ATOM: - case PMC_CPU_INTEL_ATOM_SILVERMONT: - case PMC_CPU_INTEL_ATOM_GOLDMONT: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_CORE: - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - case PMC_CPU_INTEL_COREI7: - case PMC_CPU_INTEL_NEHALEM_EX: - case PMC_CPU_INTEL_IVYBRIDGE: - case PMC_CPU_INTEL_SANDYBRIDGE: - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - case PMC_CPU_INTEL_HASWELL: - case PMC_CPU_INTEL_HASWELL_XEON: - MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF); - error = pmc_core_initialize(pmc_mdep, ncpus, verov); - break; - - default: - KASSERT(0, ("[intel,%d] Unknown CPU type", __LINE__)); - } + MPASS(nclasses >= PMC_MDEP_CLASS_INDEX_IAF); + error = pmc_core_initialize(pmc_mdep, ncpus, verov); if (error) { pmc_tsc_finalize(pmc_mdep); goto error; @@ -338,34 +312,7 @@ pmc_intel_finalize(struct pmc_mdep *md) { pmc_tsc_finalize(md); - switch (md->pmd_cputype) { - case PMC_CPU_INTEL_ATOM: - case PMC_CPU_INTEL_ATOM_SILVERMONT: - case PMC_CPU_INTEL_ATOM_GOLDMONT: - case PMC_CPU_INTEL_BROADWELL: - case PMC_CPU_INTEL_BROADWELL_XEON: - case PMC_CPU_INTEL_SKYLAKE_XEON: - case PMC_CPU_INTEL_SKYLAKE: - case PMC_CPU_INTEL_ICELAKE: - case PMC_CPU_INTEL_ICELAKE_XEON: - case PMC_CPU_INTEL_CORE: - case PMC_CPU_INTEL_CORE2: - case PMC_CPU_INTEL_CORE2EXTREME: - case PMC_CPU_INTEL_COREI7: - case PMC_CPU_INTEL_NEHALEM_EX: - case PMC_CPU_INTEL_HASWELL: - case PMC_CPU_INTEL_HASWELL_XEON: - case PMC_CPU_INTEL_IVYBRIDGE: - case PMC_CPU_INTEL_SANDYBRIDGE: - case PMC_CPU_INTEL_WESTMERE: - case PMC_CPU_INTEL_WESTMERE_EX: - case PMC_CPU_INTEL_SANDYBRIDGE_XEON: - case PMC_CPU_INTEL_IVYBRIDGE_XEON: - pmc_core_finalize(md); - break; - default: - KASSERT(0, ("[intel,%d] unknown CPU type", __LINE__)); - } + pmc_core_finalize(md); /* * Uncore. diff --git a/sys/sys/pmc.h b/sys/sys/pmc.h index 31b0e6094e04..95107771694a 100644 --- a/sys/sys/pmc.h +++ b/sys/sys/pmc.h @@ -113,6 +113,7 @@ extern char pmc_cpuid[PMC_CPUID_LEN]; __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ + __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \