From nobody Fri Jan 28 20:39:17 2022 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 2BCDB1993581; Fri, 28 Jan 2022 20:39:18 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Jlq7V0TLDz4d71; Fri, 28 Jan 2022 20:39:18 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1643402358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=UMqYPo3FtmhdiRdR9k9uT5dM8KDUJ8/WLcxtXI/TZhQ=; b=U+CAwMU0H84xMTeY7pOQqkWAB77QMGHgD+4B1Jg5hik3uLhDdmplMviyEIuS3Zd8WjMXUK 9SIYrGPS5NwR5bgD8Q/TDwq/xapBe57RBMeVlgqopsgim/CqjsX1vXML9n8lQai+JAHedz R0UlhPNHnlG7tJqmr81lPSutIWaR5CENfz1n+0IEjZRpTbhHdJitDMoy5fYgM3ygKs/hBP Qh2au4mMtx+OhuIeo2xvxzVLornIKM24QlHirhotfIpaBnIq6DlLfwG+BGdL0LbDkBwI/v /jScGhCuagi6iHF9f8ZjrRoOVblxa010xow+4Wiw9+RVcZvL6RRfkdvIx5GG3g== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id D78E8C52; Fri, 28 Jan 2022 20:39:17 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 20SKdHJ7063131; Fri, 28 Jan 2022 20:39:17 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 20SKdH6c063130; Fri, 28 Jan 2022 20:39:17 GMT (envelope-from git) Date: Fri, 28 Jan 2022 20:39:17 GMT Message-Id: <202201282039.20SKdH6c063130@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Mitchell Horne Subject: git: 99830f702d8d - main - libpmc: remove mips support List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 99830f702d8deab33c8704b4d2747385e5c8aac2 Auto-Submitted: auto-generated ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1643402358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=UMqYPo3FtmhdiRdR9k9uT5dM8KDUJ8/WLcxtXI/TZhQ=; b=EoLIHgfMqoLf9eU/cY3S1vlF/XnCCe98gn9OOKvX0pHizM1NQoAEPqrgjCbDHMKCI+LxWt OlC7xzlZq4PE6Nx6c5EFZkjc9BaywF3gN+eoox1SkTRgS/gjiffc0CA2+gSaD0hiN2kJuP J+iFes2uWQCOoJmFXfs2OYO+Mf9l/WF7zXcH2mf9rqp8DuvxR3XcN2ex5olIDjixh9CKQc a1/BIrBHDSqDpfBgdVMi43M6RVpkI6pyMuoA3qofptZ/iYXZLpKOWXZeXwzW2x+B74N4pZ FSbkEUimWdQtMZVtEFLEibMtxOJHxhl9DfcOqCGieUGz0DmY5uJTJqip6HQOjA== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1643402358; a=rsa-sha256; cv=none; b=BaaGKBvuNeZixtMulPq5cHXb6uizVQAogfky3Axp8FxKfT/BGvvwQymSRv4gT/3Qjw505t u9Eyjn/wF8M5D/m9gNKA2MRupC0SXuresv9jTnL64wwTDvQnCNZvojdZwAhWEN7Nce7S3X JcIUjULBrvE2G/BIYkovgEVQNP/HIK7lmp+sOncNr8ELc2bo7glhI+30KihiqwXw8L0G5e PcZbqMCjUPga8+SlPww5ly1zuU0G8en3lFqfFszwwgL+u66gCq+eyzhjJm0ml8R5RQAiNB DLbPWaYtH7FUCSh/f+xYas/E0bHG+IxyCIqc3iHVBP2RICM8EHNtl/ZB7+EGwg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=99830f702d8deab33c8704b4d2747385e5c8aac2 commit 99830f702d8deab33c8704b4d2747385e5c8aac2 Author: Mitchell Horne AuthorDate: 2022-01-28 20:34:36 +0000 Commit: Mitchell Horne CommitDate: 2022-01-28 20:35:32 +0000 libpmc: remove mips support Bye bye! Reviewed by: imp, emaste Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D34083 --- ObsoleteFiles.inc | 4 + lib/libpmc/Makefile | 2 - lib/libpmc/libpmc.c | 118 -------------- lib/libpmc/pmc.3 | 2 - lib/libpmc/pmc.mips24k.3 | 409 ----------------------------------------------- lib/libpmc/pmc.octeon.3 | 249 ----------------------------- 6 files changed, 4 insertions(+), 780 deletions(-) diff --git a/ObsoleteFiles.inc b/ObsoleteFiles.inc index dc065d970478..56e94d07855b 100644 --- a/ObsoleteFiles.inc +++ b/ObsoleteFiles.inc @@ -52,6 +52,10 @@ # xargs -n1 | sort | uniq -d; # done +# 20220128: mips pmc events removed +OLD_FILES+=usr/share/man/man3/pmc.mips24k.3 +OLD_FILES+=usr/share/man/man3/pmc.octeon.3 + # 20220127: terasic_mtl.4 removed OLD_FILES+=usr/share/man/man4/terasic_mtl.4.gz diff --git a/lib/libpmc/Makefile b/lib/libpmc/Makefile index 2ef0d288064c..8d884366eed7 100644 --- a/lib/libpmc/Makefile +++ b/lib/libpmc/Makefile @@ -81,8 +81,6 @@ MAN+= pmc.ivybridge.3 MAN+= pmc.ivybridgexeon.3 MAN+= pmc.k7.3 MAN+= pmc.k8.3 -MAN+= pmc.mips24k.3 -MAN+= pmc.octeon.3 MAN+= pmc.sandybridge.3 MAN+= pmc.sandybridgeuc.3 MAN+= pmc.sandybridgexeon.3 diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c index 4df888f497c0..bf1b4adfa1d3 100644 --- a/lib/libpmc/libpmc.c +++ b/lib/libpmc/libpmc.c @@ -66,10 +66,6 @@ static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec, static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); #endif -#if defined(__mips__) -static int mips_allocate_pmc(enum pmc_event _pe, char* ctrspec, - struct pmc_op_pmcallocate *_pmc_config); -#endif /* __mips__ */ static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec, struct pmc_op_pmcallocate *_pmc_config); @@ -138,10 +134,6 @@ PMC_CLASSDEP_TABLE(iaf, IAF); PMC_CLASSDEP_TABLE(k8, K8); PMC_CLASSDEP_TABLE(armv7, ARMV7); PMC_CLASSDEP_TABLE(armv8, ARMV8); -PMC_CLASSDEP_TABLE(beri, BERI); -PMC_CLASSDEP_TABLE(mips24k, MIPS24K); -PMC_CLASSDEP_TABLE(mips74k, MIPS74K); -PMC_CLASSDEP_TABLE(octeon, OCTEON); PMC_CLASSDEP_TABLE(ppc7450, PPC7450); PMC_CLASSDEP_TABLE(ppc970, PPC970); PMC_CLASSDEP_TABLE(e500, E500); @@ -209,12 +201,6 @@ PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64); PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64); PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64); #endif -#if defined(__mips__) -PMC_CLASS_TABLE_DESC(beri, BERI, beri, mips); -PMC_CLASS_TABLE_DESC(mips24k, MIPS24K, mips24k, mips); -PMC_CLASS_TABLE_DESC(mips74k, MIPS74K, mips74k, mips); -PMC_CLASS_TABLE_DESC(octeon, OCTEON, octeon, mips); -#endif /* __mips__ */ #if defined(__powerpc__) PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc); PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc); @@ -780,64 +766,6 @@ arm64_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, } #endif -#if defined(__mips__) - -static struct pmc_event_alias beri_aliases[] = { - EV_ALIAS("instructions", "INST"), - EV_ALIAS(NULL, NULL) -}; - -static struct pmc_event_alias mips24k_aliases[] = { - EV_ALIAS("instructions", "INSTR_EXECUTED"), - EV_ALIAS("branches", "BRANCH_COMPLETED"), - EV_ALIAS("branch-mispredicts", "BRANCH_MISPRED"), - EV_ALIAS(NULL, NULL) -}; - -static struct pmc_event_alias mips74k_aliases[] = { - EV_ALIAS("instructions", "INSTR_EXECUTED"), - EV_ALIAS("branches", "BRANCH_INSNS"), - EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCH_INSNS"), - EV_ALIAS(NULL, NULL) -}; - -static struct pmc_event_alias octeon_aliases[] = { - EV_ALIAS("instructions", "RET"), - EV_ALIAS("branches", "BR"), - EV_ALIAS("branch-mispredicts", "BRMIS"), - EV_ALIAS(NULL, NULL) -}; - -#define MIPS_KW_OS "os" -#define MIPS_KW_USR "usr" -#define MIPS_KW_ANYTHREAD "anythread" - -static int -mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused, - struct pmc_op_pmcallocate *pmc_config __unused) -{ - char *p; - - (void) pe; - - pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); - - while ((p = strsep(&ctrspec, ",")) != NULL) { - if (KWMATCH(p, MIPS_KW_OS)) - pmc_config->pm_caps |= PMC_CAP_SYSTEM; - else if (KWMATCH(p, MIPS_KW_USR)) - pmc_config->pm_caps |= PMC_CAP_USER; - else if (KWMATCH(p, MIPS_KW_ANYTHREAD)) - pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM); - else - return (-1); - } - - return (0); -} - -#endif /* __mips__ */ - #if defined(__powerpc__) static struct pmc_event_alias ppc7450_aliases[] = { @@ -1211,22 +1139,6 @@ pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames, break; } break; - case PMC_CLASS_BERI: - ev = beri_event_table; - count = PMC_EVENT_TABLE_SIZE(beri); - break; - case PMC_CLASS_MIPS24K: - ev = mips24k_event_table; - count = PMC_EVENT_TABLE_SIZE(mips24k); - break; - case PMC_CLASS_MIPS74K: - ev = mips74k_event_table; - count = PMC_EVENT_TABLE_SIZE(mips74k); - break; - case PMC_CLASS_OCTEON: - ev = octeon_event_table; - count = PMC_EVENT_TABLE_SIZE(octeon); - break; case PMC_CLASS_PPC7450: ev = ppc7450_event_table; count = PMC_EVENT_TABLE_SIZE(ppc7450); @@ -1426,24 +1338,6 @@ pmc_init(void) pmc_class_table[n] = &cortex_a76_class_table_descr; break; #endif -#if defined(__mips__) - case PMC_CPU_MIPS_BERI: - PMC_MDEP_INIT(beri); - pmc_class_table[n] = &beri_class_table_descr; - break; - case PMC_CPU_MIPS_24K: - PMC_MDEP_INIT(mips24k); - pmc_class_table[n] = &mips24k_class_table_descr; - break; - case PMC_CPU_MIPS_74K: - PMC_MDEP_INIT(mips74k); - pmc_class_table[n] = &mips74k_class_table_descr; - break; - case PMC_CPU_MIPS_OCTEON: - PMC_MDEP_INIT(octeon); - pmc_class_table[n] = &octeon_class_table_descr; - break; -#endif /* __mips__ */ #if defined(__powerpc__) case PMC_CPU_PPC_7450: PMC_MDEP_INIT(ppc7450); @@ -1570,18 +1464,6 @@ _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu) default: /* Unknown CPU type. */ break; } - } else if (pe >= PMC_EV_BERI_FIRST && pe <= PMC_EV_BERI_LAST) { - ev = beri_event_table; - evfence = beri_event_table + PMC_EVENT_TABLE_SIZE(beri); - } else if (pe >= PMC_EV_MIPS24K_FIRST && pe <= PMC_EV_MIPS24K_LAST) { - ev = mips24k_event_table; - evfence = mips24k_event_table + PMC_EVENT_TABLE_SIZE(mips24k); - } else if (pe >= PMC_EV_MIPS74K_FIRST && pe <= PMC_EV_MIPS74K_LAST) { - ev = mips74k_event_table; - evfence = mips74k_event_table + PMC_EVENT_TABLE_SIZE(mips74k); - } else if (pe >= PMC_EV_OCTEON_FIRST && pe <= PMC_EV_OCTEON_LAST) { - ev = octeon_event_table; - evfence = octeon_event_table + PMC_EVENT_TABLE_SIZE(octeon); } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) { ev = ppc7450_event_table; evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450); diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3 index 4bf2907db129..3325cb1e3d40 100644 --- a/lib/libpmc/pmc.3 +++ b/lib/libpmc/pmc.3 @@ -491,8 +491,6 @@ API is .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , -.Xr pmc.mips24k 3 , -.Xr pmc.octeon 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , diff --git a/lib/libpmc/pmc.mips24k.3 b/lib/libpmc/pmc.mips24k.3 deleted file mode 100644 index 52761d5db751..000000000000 --- a/lib/libpmc/pmc.mips24k.3 +++ /dev/null @@ -1,409 +0,0 @@ -.\" Copyright (c) 2010 George Neville-Neil. All rights reserved. -.\" -.\" Redistribution and use in source and binary forms, with or without -.\" modification, are permitted provided that the following conditions -.\" are met: -.\" 1. Redistributions of source code must retain the above copyright -.\" notice, this list of conditions and the following disclaimer. -.\" 2. Redistributions in binary form must reproduce the above copyright -.\" notice, this list of conditions and the following disclaimer in the -.\" documentation and/or other materials provided with the distribution. -.\" -.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -.\" SUCH DAMAGE. -.\" -.\" $FreeBSD$ -.\" -.Dd March 24, 2012 -.Dt PMC.MIPS24K 3 -.Os -.Sh NAME -.Nm pmc.mips24k -.Nd measurement events for -.Tn MIPS24K -family CPUs -.Sh LIBRARY -.Lb libpmc -.Sh SYNOPSIS -.In pmc.h -.Sh DESCRIPTION -MIPS PMCs are present in MIPS -.Tn "24k" -and other processors in the MIPS family. -.Pp -There are two counters supported by the hardware and each is 32 bits -wide. -.Pp -MIPS PMCs are documented in -.Rs -.%B "MIPS32 24K Processor Core Family Software User's Manual" -.%D December 2008 -.%Q "MIPS Technologies Inc." -.Re -.Ss Event Specifiers (Programmable PMCs) -MIPS programmable PMCs support the following events: -.Bl -tag -width indent -.It Li CYCLE -.Pq Event 0, Counter 0/1 -Total number of cycles. -The performance counters are clocked by the -top-level gated clock. -If the core is built with that clock gater -present, none of the counters will increment while the clock is -stopped - due to a WAIT instruction. -.It Li INSTR_EXECUTED -.Pq Event 1, Counter 0/1 -Total number of instructions completed. -.It Li BRANCH_COMPLETED -.Pq Event 2, Counter 0 -Total number of branch instructions completed. -.It Li BRANCH_MISPRED -.Pq Event 2, Counter 1 -Counts all branch instructions which completed, but were mispredicted. -.It Li RETURN -.Pq Event 3, Counter 0 -Counts all JR R31 instructions completed. -.It Li RETURN_MISPRED -.Pq Event 3, Counter 1 -Counts all JR $31 instructions which completed, used the RPS for a prediction, but were mispredicted. -.It Li RETURN_NOT_31 -.Pq Event 4, Counter 0 -Counts all JR $xx (not $31) and JALR instructions (indirect jumps). -.It Li RETURN_NOTPRED -.Pq Event 4, Counter 1 -If RPS use is disabled, JR $31 will not be predicted. -.It Li ITLB_ACCESS -.Pq Event 5, Counter 0 -Counts ITLB accesses that are due to fetches showing up in the -instruction fetch stage of the pipeline and which do not use a fixed -mapping or are not in unmapped space. -If an address is fetched twice from the pipe (as in the case of a -cache miss), that instruction willcount as 2 ITLB accesses. -Since each fetch gets us 2 instructions,there is one access marked per double -word. -.It Li ITLB_MISS -.Pq Event 5, Counter 1 -Counts all misses in the ITLB except ones that are on the back of another -miss. -We cannot process back to back misses and thus those are -ignored. -They are also ignored if there is some form of address error. -.It Li DTLB_ACCESS -.Pq Event 6, Counter 0 -Counts DTLB access including those in unmapped address spaces. -.It Li DTLB_MISS -.Pq Event 6, Counter 1 -Counts DTLB misses. -Back to back misses that result in only one DTLB -entry getting refilled are counted as a single miss. -.It Li JTLB_IACCESS -.Pq Event 7, Counter 0 -Instruction JTLB accesses are counted exactly the same as ITLB misses. -.It Li JTLB_IMISS -.Pq Event 7, Counter 1 -Counts instruction JTLB accesses that result in no match or a match on -an invalid translation. -.It Li JTLB_DACCESS -.Pq Event 8, Counter 0 -Data JTLB accesses. -.It Li JTLB_DMISS -.Pq Event 8, Counter 1 -Counts data JTLB accesses that result in no match or a match on an invalid translation. -.It Li IC_FETCH -.Pq Event 9, Counter 0 -Counts every time the instruction cache is accessed. -All replays, -wasted fetches etc. are counted. -For example, following a branch, even though the prediction is taken, -the fall through access is counted. -.It Li IC_MISS -.Pq Event 9, Counter 1 -Counts all instruction cache misses that result in a bus request. -.It Li DC_LOADSTORE -.Pq Event 10, Counter 0 -Counts cached loads and stores. -.It Li DC_WRITEBACK -.Pq Event 10, Counter 1 -Counts cache lines written back to memory due to replacement or cacheops. -.It Li DC_MISS -.Pq Event 11, Counter 0/1 -Counts loads and stores that miss in the cache -.It Li LOAD_MISS -.Pq Event 13, Counter 0 -Counts number of cacheable loads that miss in the cache. -.It Li STORE_MISS -.Pq Event 13, Counter 1 -Counts number of cacheable stores that miss in the cache. -.It Li INTEGER_COMPLETED -.Pq Event 14, Counter 0 -Non-floating point, non-Coprocessor 2 instructions. -.It Li FP_COMPLETED -.Pq Event 14, Counter 1 -Floating point instructions completed. -.It Li LOAD_COMPLETED -.Pq Event 15, Counter 0 -Integer and co-processor loads completed. -.It Li STORE_COMPLETED -.Pq Event 15, Counter 1 -Integer and co-processor stores completed. -.It Li BARRIER_COMPLETED -.Pq Event 16, Counter 0 -Direct jump (and link) instructions completed. -.It Li MIPS16_COMPLETED -.Pq Event 16, Counter 1 -MIPS16c instructions completed. -.It Li NOP_COMPLETED -.Pq Event 17, Counter 0 -NOPs completed. -This includes all instructions that normally write to a general -purpose register, but where the destination register was set to r0. -.It Li INTEGER_MULDIV_COMPLETED -.Pq Event 17, Counter 1 -Integer multiply and divide instructions completed. (MULxx, DIVx, MADDx, MSUBx). -.It Li RF_STALL -.Pq Event 18, Counter 0 -Counts the total number of cycles where no instructions are issued -from the IFU to ALU (the RF stage does not advance) which includes -both of the previous two events. -The RT_STALL is different than the sum of them though because cycles -when both stalls are active will only be counted once. -.It Li INSTR_REFETCH -.Pq Event 18, Counter 1 -replay traps (other than uTLB) -.It Li STORE_COND_COMPLETED -.Pq Event 19, Counter 0 -Conditional stores completed. -Counts all events, including failed stores. -.It Li STORE_COND_FAILED -.Pq Event 19, Counter 1 -Conditional store instruction that did not update memory. -Note: While this event and the SC instruction count event can be configured to -count in specific operating modes, the timing of the events is much -different and the observed operating mode could change between them, -causing some inaccuracy in the measured ratio. -.It Li ICACHE_REQUESTS -.Pq Event 20, Counter 0 -Note that this only counts PREFs that are actually attempted. -PREFs to uncached addresses or ones with translation errors are not counted -.It Li ICACHE_HIT -.Pq Event 20, Counter 1 -Counts PREF instructions that hit in the cache -.It Li L2_WRITEBACK -.Pq Event 21, Counter 0 -Counts cache lines written back to memory due to replacement or cacheops. -.It Li L2_ACCESS -.Pq Event 21, Counter 1 -Number of accesses to L2 Cache. -.It Li L2_MISS -.Pq Event 22, Counter 0 -Number of accesses that missed in the L2 cache. -.It Li L2_ERR_CORRECTED -.Pq Event 22, Counter 1 -Single bit errors in L2 Cache that were detected and corrected. -.It Li EXCEPTIONS -.Pq Event 23, Counter 0 -Any type of exception taken. -.It Li RF_CYCLES_STALLED -.Pq Event 24, Counter 0 -Counts cycles where the LSU is in fixup and cannot accept a new -instruction from the ALU. -Fixups are replays within the LSU that occur when an instruction needs -to re-access the cache or the DTLB. -.It Li IFU_CYCLES_STALLED -.Pq Event 25, Counter 0 -Counts the number of cycles where the fetch unit is not providing a -valid instruction to the ALU. -.It Li ALU_CYCLES_STALLED -.Pq Event 25, Counter 1 -Counts the number of cycles where the ALU pipeline cannot advance. -.It Li UNCACHED_LOAD -.Pq Event 33, Counter 0 -Counts uncached and uncached accelerated loads. -.It Li UNCACHED_STORE -.Pq Event 33, Counter 1 -Counts uncached and uncached accelerated stores. -.It Li CP2_REG_TO_REG_COMPLETED -.Pq Event 35, Counter 0 -Co-processor 2 register to register instructions completed. -.It Li MFTC_COMPLETED -.Pq Event 35, Counter 1 -Co-processor 2 move to and from instructions as well as loads and stores. -.It Li IC_BLOCKED_CYCLES -.Pq Event 37, Counter 0 -Cycles when IFU stalls because an instruction miss caused the IFU not -to have any runnable instructions. -Ignores the stalls due to ITLB misses as well as the 4 cycles -following a redirect. -.It Li DC_BLOCKED_CYCLES -.Pq Event 37, Counter 1 -Counts all cycles where integer pipeline waits on Load return data due -to a D-cache miss. -The LSU can signal a "long stall" on a D-cache misses, in which case -the waiting TC might be rescheduled so other TCs can execute -instructions till the data returns. -.It Li L2_IMISS_STALL_CYCLES -.Pq Event 38, Counter 0 -Cycles where the main pipeline is stalled waiting for a SYNC to complete. -.It Li L2_DMISS_STALL_CYCLES -.Pq Event 38, Counter 1 -Cycles where the main pipeline is stalled because of an index conflict -in the Fill Store Buffer. -.It Li DMISS_CYCLES -.Pq Event 39, Counter 0 -Data miss is outstanding, but not necessarily stalling the pipeline. -The difference between this and D$ miss stall cycles can show the gain -from non-blocking cache misses. -.It Li L2_MISS_CYCLES -.Pq Event 39, Counter 1 -L2 miss is outstanding, but not necessarily stalling the pipeline. -.It Li UNCACHED_BLOCK_CYCLES -.Pq Event 40, Counter 0 -Cycles where the processor is stalled on an uncached fetch, load, or store. -.It Li MDU_STALL_CYCLES -.Pq Event 41, Counter 0 -Cycles where the processor is stalled on an uncached fetch, load, or store. -.It Li FPU_STALL_CYCLES -.Pq Event 41, Counter 1 -Counts all cycles where integer pipeline waits on FPU return data. -.It Li CP2_STALL_CYCLES -.Pq Event 42, Counter 0 -Counts all cycles where integer pipeline waits on CP2 return data. -.It Li COREXTEND_STALL_CYCLES -.Pq Event 42, Counter 1 -Counts all cycles where integer pipeline waits on CorExtend return data. -.It Li ISPRAM_STALL_CYCLES -.Pq Event 43, Counter 0 -Count all pipeline bubbles that are a result of multicycle ISPRAM -access. -Pipeline bubbles are defined as all cycles that IFU doesn't present an -instruction to ALU. -The four cycles after a redirect are not counted. -.It Li DSPRAM_STALL_CYCLES -.Pq Event 43, Counter 1 -Counts stall cycles created by an instruction waiting for access to DSPRAM. -.It Li CACHE_STALL_CYCLES -.Pq Event 44, Counter 0 -Counts all cycles the where pipeline is stalled due to CACHE -instructions. -Includes cycles where CACHE instructions themselves are -stalled in the ALU, and cycles where CACHE instructions cause -subsequent instructions to be stalled. -.It Li LOAD_TO_USE_STALLS -.Pq Event 45, Counter 0 -Counts all cycles where integer pipeline waits on Load return data. -.It Li BASE_MISPRED_STALLS -.Pq Event 45, Counter 1 -Counts stall cycles due to skewed ALU where the bypass to the address -generation takes an extra cycle. -.It Li CPO_READ_STALLS -.Pq Event 46, Counter 0 -Counts all cycles where integer pipeline waits on return data from -MFC0, RDHWR instructions. -.It Li BRANCH_MISPRED_CYCLES -.Pq Event 46, Counter 1 -This counts the number of cycles from a mispredicted branch until the -next non-delay slot instruction executes. -.It Li IFETCH_BUFFER_FULL -.Pq Event 48, Counter 0 -Counts the number of times an instruction cache miss was detected, but -both fill buffers were already allocated. -.It Li FETCH_BUFFER_ALLOCATED -.Pq Event 48, Counter 1 -Number of cycles where at least one of the IFU fill buffers is -allocated (miss pending). -.It Li EJTAG_ITRIGGER -.Pq Event 49, Counter 0 -Number of times an EJTAG Instruction Trigger Point condition matched. -.It Li EJTAG_DTRIGGER -.Pq Event 49, Counter 1 -Number of times an EJTAG Data Trigger Point condition matched. -.It Li FSB_LT_QUARTER -.Pq Event 50, Counter 0 -Fill store buffer less than one quarter full. -.It Li FSB_QUARTER_TO_HALF -.Pq Event 50, Counter 1 -Fill store buffer between one quarter and one half full. -.It Li FSB_GT_HALF -.Pq Event 51, Counter 0 -Fill store buffer more than half full. -.It Li FSB_FULL_PIPELINE_STALLS -.Pq Event 51, Counter 1 -Cycles where the pipeline is stalled because the Fill-Store Buffer in LSU is full. -.It Li LDQ_LT_QUARTER -.Pq Event 52, Counter 0 -Load data queue less than one quarter full. -.It Li LDQ_QUARTER_TO_HALF -.Pq Event 52, Counter 1 -Load data queue between one quarter and one half full. -.It Li LDQ_GT_HALF -.Pq Event 53, Counter 0 -Load data queue more than one half full. -.It Li LDQ_FULL_PIPELINE_STALLS -.Pq Event 53, Counter 1 -Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full. -.It Li WBB_LT_QUARTER -.Pq Event 54, Counter 0 -Write back buffer less than one quarter full. -.It Li WBB_QUARTER_TO_HALF -.Pq Event 54, Counter 1 -Write back buffer between one quarter and one half full. -.It Li WBB_GT_HALF -.Pq Event 55, Counter 0 -Write back buffer more than one half full. -.It Li WBB_FULL_PIPELINE_STALLS -.Pq Event 55 Counter 1 -Cycles where the pipeline is stalled because the Load Data Queue in the LSU is full. -.It Li REQUEST_LATENCY -.Pq Event 61, Counter 0 -Measures latency from miss detection until critical dword of response -is returned, Only counts for cacheable reads. -.It Li REQUEST_COUNT -.Pq Event 61, Counter 1 -Counts number of cacheable read requests used for previous latency counter. -.El -.Ss Event Name Aliases -The following table shows the mapping between the PMC-independent -aliases supported by -.Lb libpmc -and the underlying hardware events used. -.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" -.It Em Alias Ta Em Event -.It Li instructions Ta Li INSTR_EXECUTED -.It Li branches Ta Li BRANCH_COMPLETED -.It Li branch-mispredicts Ta Li BRANCH_MISPRED -.El -.Sh SEE ALSO -.Xr pmc 3 , -.Xr pmc.atom 3 , -.Xr pmc.core 3 , -.Xr pmc.iaf 3 , -.Xr pmc.k7 3 , -.Xr pmc.k8 3 , -.Xr pmc.octeon 3 , -.Xr pmc.soft 3 , -.Xr pmc.tsc 3 , -.Xr pmc_cpuinfo 3 , -.Xr pmclog 3 , -.Xr hwpmc 4 -.Sh HISTORY -The -.Nm pmc -library first appeared in -.Fx 6.0 . -.Sh AUTHORS -.An -nosplit -The -.Lb libpmc -library was written by -.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . -MIPS support was added by -.An George Neville-Neil Aq Mt gnn@FreeBSD.org . diff --git a/lib/libpmc/pmc.octeon.3 b/lib/libpmc/pmc.octeon.3 deleted file mode 100644 index 43d204f164e6..000000000000 --- a/lib/libpmc/pmc.octeon.3 +++ /dev/null @@ -1,249 +0,0 @@ -.\" Copyright (c) 2010 George Neville-Neil. All rights reserved. -.\" -.\" Redistribution and use in source and binary forms, with or without -.\" modification, are permitted provided that the following conditions -.\" are met: -.\" 1. Redistributions of source code must retain the above copyright -.\" notice, this list of conditions and the following disclaimer. -.\" 2. Redistributions in binary form must reproduce the above copyright -.\" notice, this list of conditions and the following disclaimer in the -.\" documentation and/or other materials provided with the distribution. -.\" -.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -.\" SUCH DAMAGE. -.\" -.\" $FreeBSD$ -.\" -.Dd March 24, 2012 -.Dt PMC.OCTEON 3 -.Os -.Sh NAME -.Nm pmc.octeon -.Nd measurement events for -.Tn Octeon -family CPUs -.Sh LIBRARY -.Lb libpmc -.Sh SYNOPSIS -.In pmc.h -.Sh DESCRIPTION -There are two counters per core supported by the hardware and each is 64 bits -wide. -.Ss Event Specifiers (Programmable PMCs) -MIPS programmable PMCs support the following events: -.Bl -tag -width indent -.It Li CLK -.Pq Event 1 -Conditionally clocked cycles (as opposed to count/cvm_count which count even with no clocks) -.It Li ISSUE -.Pq Event 2 -Instructions issued but not retired -.It Li RET -.Pq Event 3 -Instructions retired -.It Li NISSUE -.Pq Event 4 -Cycles no issue -.It Li SISSUE -.Pq Event 5 -Cycles single issue -.It Li DISSUE -.Pq Event 6 -Cycles dual issue -.It Li IFI -.Pq Event 7 -Cycle ifetch issued (but not necessarily commit to pp_mem) -.It Li BR -.Pq Event 8 -Branches retired -.It Li BRMIS -.Pq Event 9 -Branch mispredicts -.It Li J -.Pq Event 10 -Jumps retired -.It Li JMIS -.Pq Event 11 -Jumps mispredicted -.It Li REPLAY -.Pq Event 12 -Mem Replays -.It Li IUNA -.Pq Event 13 -Cycles idle due to unaligned_replays -.It Li TRAP -.Pq Event 14 -trap_6a signal -.It Li UULOAD -.Pq Event 16 -Unexpected unaligned loads (REPUN=1) -.It Li UUSTORE -.Pq Event 17 -Unexpected unaligned store (REPUN=1) -.It Li ULOAD -.Pq Event 18 -Unaligned loads (REPUN=1 or USEUN=1) -.It Li USTORE -.Pq Event 19 -Unaligned store (REPUN=1 or USEUN=1) -.It Li EC -.Pq Event 20 -Exec clocks(must set CvmCtl[DISCE] for accurate timing) -.It Li MC -.Pq Event 21 -Mul clocks(must set CvmCtl[DISCE] for accurate timing) -.It Li CC -.Pq Event 22 -Crypto clocks(must set CvmCtl[DISCE] for accurate timing) -.It Li CSRC -.Pq Event 23 -Issue_csr clocks(must set CvmCtl[DISCE] for accurate timing) -.It Li CFETCH -.Pq Event 24 -Icache committed fetches (demand+prefetch) -.It Li CPREF -.Pq Event 25 -Icache committed prefetches -.It Li ICA -.Pq Event 26 -Icache aliases -.It Li II -.Pq Event 27 -Icache invalidates -.It Li IP -.Pq Event 28 -Icache parity error -.It Li CIMISS -.Pq Event 29 -Cycles idle due to imiss (must set CvmCtl[DISCE] for accurate timing) -.It Li WBUF -.Pq Event 32 -Number of write buffer entries created -.It Li WDAT -.Pq Event 33 -Number of write buffer data cycles used (may need to set CvmCtl[DISCE] for accurate counts) -.It Li WBUFLD -.Pq Event 34 -Number of write buffer entries forced out by loads -.It Li WBUFFL -.Pq Event 35 -Number of cycles that there was no available write buffer entry (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) -.It Li WBUFTR -.Pq Event 36 -Number of stores that found no available write buffer entries -.It Li BADD -.Pq Event 37 -Number of address bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) -.It Li BADDL2 -.Pq Event 38 -Number of address bus cycles not reflected (i.e. destined for L2) (may need to set CvmCtl[DISCE] for accurate counts) -.It Li BFILL -.Pq Event 39 -Number of fill bus cycles used (may need to set CvmCtl[DISCE] for accurate counts) -.It Li DDIDS -.Pq Event 40 -Number of Dstream DIDs created -.It Li IDIDS -.Pq Event 41 -Number of Istream DIDs created -.It Li DIDNA -.Pq Event 42 -Number of cycles that no DIDs were available (may need to set CvmCtl[DISCE] and CvmMemCtl[MCLK] for accurate counts) -.It Li LDS -.Pq Event 43 -Number of load issues -.It Li LMLDS -.Pq Event 44 -Number of local memory load -.It Li IOLDS -.Pq Event 45 -Number of I/O load issues -.It Li DMLDS -.Pq Event 46 -Number of loads that were not prefetches and missed in the cache -.It Li STS -.Pq Event 48 -Number of store issues -.It Li LMSTS -.Pq Event 49 -Number of local memory store issues -.It Li IOSTS -.Pq Event 50 -Number of I/O store issues -.It Li IOBDMA -.Pq Event 51 -Number of IOBDMAs -.It Li DTLB -.Pq Event 53 -Number of dstream TLB refill, invalid, or modified exceptions -.It Li DTLBAD -.Pq Event 54 -Number of dstream TLB address errors -.It Li ITLB -.Pq Event 55 -Number of istream TLB refill, invalid, or address error exceptions -.It Li SYNC -.Pq Event 56 -Number of SYNC stall cycles (may need to set CvmCtl[DISCE] for accurate counts) -.It Li SYNCIOB -.Pq Event 57 -Number of SYNCIOBDMA stall cycles (may need to set CvmCtl[DISCE] for accurate counts) -.It Li SYNCW -.Pq Event 58 -Number of SYNCWs -.It Li ERETMIS -.Pq Event 64 -D/eret mispredicts (CN63XX specific) -.It Li LIKMIS -.Pq Event 65 -Branch likely mispredicts (CN63XX specific) -.It Li HAZTR -.Pq Event 66 -Hazard traps due to *MTC0 to CvmCtl, Perf counter control, EntryHi, or CvmMemCtl registers (CN63XX specific) -.El -.Ss Event Name Aliases -The following table shows the mapping between the PMC-independent -aliases supported by -.Lb libpmc -and the underlying hardware events used. -.Bl -column "branch-mispredicts" "cpu_clk_unhalted.core_p" -.It Em Alias Ta Em Event -.It Li instructions Ta Li RET -.It Li branches Ta Li BR -.It Li branch-mispredicts Ta Li BS -.El -.Sh SEE ALSO -.Xr pmc 3 , -.Xr pmc.atom 3 , -.Xr pmc.core 3 , -.Xr pmc.iaf 3 , -.Xr pmc.k7 3 , -.Xr pmc.k8 3 , -.Xr pmc.mips24k 3 , -.Xr pmc.soft 3 , -.Xr pmc.tsc 3 , -.Xr pmc_cpuinfo 3 , -.Xr pmclog 3 , -.Xr hwpmc 4 -.Sh HISTORY -The -.Nm pmc -library first appeared in -.Fx 6.0 . -.Sh AUTHORS -.An -nosplit -The -.Lb libpmc -library was written by -.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org . -MIPS support was added by -.An George Neville-Neil Aq Mt gnn@FreeBSD.org .