From nobody Tue Nov 02 10:34:53 2021 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 2CA931822C29; Tue, 2 Nov 2021 10:34:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Hk5rG0r9hz4dQn; Tue, 2 Nov 2021 10:34:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E60D6235CF; Tue, 2 Nov 2021 10:34:53 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 1A2AYr4j024075; Tue, 2 Nov 2021 10:34:53 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 1A2AYr2C024074; Tue, 2 Nov 2021 10:34:53 GMT (envelope-from git) Date: Tue, 2 Nov 2021 10:34:53 GMT Message-Id: <202111021034.1A2AYr2C024074@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Michal Meloun Subject: git: a670e1c13a52 - main - arm: Fix handling of undefined instruction aborts in THUMB2 mode. List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-dev-commits-src-all@freebsd.org X-BeenThere: dev-commits-src-all@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mmel X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: a670e1c13a522df4fb8c63bb023b88b1d65de797 Auto-Submitted: auto-generated X-ThisMailContainsUnwantedMimeParts: N The branch main has been updated by mmel: URL: https://cgit.FreeBSD.org/src/commit/?id=a670e1c13a522df4fb8c63bb023b88b1d65de797 commit a670e1c13a522df4fb8c63bb023b88b1d65de797 Author: Michal Meloun AuthorDate: 2021-10-17 17:36:33 +0000 Commit: Michal Meloun CommitDate: 2021-11-02 10:11:44 +0000 arm: Fix handling of undefined instruction aborts in THUMB2 mode. Correctly recognize NEON/SIMD and VFP instructions in THUMB2 mode and pass these to the appropriate handler. Note that it is not necessary to filter all undefined instruction variant or register combinations, this is a job for given handler. Reported by: Robert Clausecker PR: 259187 MFC after: 2 weks --- sys/arm/arm/undefined.c | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) diff --git a/sys/arm/arm/undefined.c b/sys/arm/arm/undefined.c index 4e9a5295d338..d95b02e2bbb4 100644 --- a/sys/arm/arm/undefined.c +++ b/sys/arm/arm/undefined.c @@ -90,13 +90,25 @@ __FBSDID("$FreeBSD$"); #define ARM_COPROC_INSN(insn) (((insn) & (1 << 27)) != 0) #define ARM_VFP_INSN(insn) ((((insn) & 0xfe000000) == 0xf2000000) || \ - (((insn) & 0xff100000) == 0xf4000000)) + (((insn) & 0xff100000) == 0xf4000000)) #define ARM_COPROC(insn) (((insn) >> 8) & 0xf) -#define THUMB_32BIT_INSN(insn) ((insn) >= 0xe800) +#define THUMB_32BIT_INSN(insn) ((((insn) & 0xe000) == 0xe000) && \ + (((insn) & 0x1800) != 0)) +/* + * Coprocessor, Advanced SIMD, and + * Floating-point instructions on page A6-251 + * OP1 == 01 OR 11 + * OP2 == 1xxxxxx + */ #define THUMB_COPROC_INSN(insn) (((insn) & (3 << 26)) == (3 << 26)) -#define THUMB_COPROC_UNDEFINED(insn) (((insn) & 0x3e << 20) == 0) -#define THUMB_VFP_INSN(insn) (((insn) & (3 << 24)) == (3 << 24)) +/* + * Advanced SIMD element or structure + * load/store instructions on page A7-275 + * OP1 == 11 + * OP2 == 001xxx0 +*/ +#define THUMB_VFP_INSN(insn) (((insn) & (0x1F1 << 20)) == (0x190 << 20)) #define THUMB_COPROC(insn) (((insn) >> 8) & 0xf) #define COPROC_VFP 10 @@ -278,18 +290,13 @@ undefinedinstruction(struct trapframe *frame) fault_instruction <<= 16; fault_instruction |= *(uint16_t *)(fault_pc + 2); - /* - * Is it a Coprocessor, Advanced SIMD, or - * Floating-point instruction. - */ - if (THUMB_COPROC_INSN(fault_instruction)) { - if (THUMB_COPROC_UNDEFINED(fault_instruction)) { - /* undefined insn */ - } else if (THUMB_VFP_INSN(fault_instruction)) - coprocessor = COPROC_VFP; - else - coprocessor = - THUMB_COPROC(fault_instruction); + /* Coprocessor, Advanced SIMD and Floating-point */ + if (THUMB_COPROC_INSN(fault_instruction)) + coprocessor = THUMB_COPROC(fault_instruction); + else { + /* Advanced SIMD load/store */ + if (THUMB_VFP_INSN(fault_instruction)) + coprocessor = COPROC_VFP; /* SIMD */ } } #else