git: 00cd352efadb - main - cad/py-pymtl: update 3.1.16 → 3.1.17
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Date: Sat, 19 Sep 2026 22:42:55 UTC
The branch main has been updated by yuri:
URL: https://cgit.FreeBSD.org/ports/commit/?id=00cd352efadb9928772b9b4b97ec8ef9eb4f2124
commit 00cd352efadb9928772b9b4b97ec8ef9eb4f2124
Author: Yuri Victorovich <yuri@FreeBSD.org>
AuthorDate: 2026-09-19 19:54:18 +0000
Commit: Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2026-09-19 22:42:22 +0000
cad/py-pymtl: update 3.1.16 → 3.1.17
---
cad/py-pymtl/Makefile | 16 +++--
cad/py-pymtl/distinfo | 6 +-
...rilog_import___VerilogVerilatorImportConfigs.py | 72 +++++++++++++++++++++-
3 files changed, 83 insertions(+), 11 deletions(-)
diff --git a/cad/py-pymtl/Makefile b/cad/py-pymtl/Makefile
index 6af7d978020c..fc4b80aa7101 100644
--- a/cad/py-pymtl/Makefile
+++ b/cad/py-pymtl/Makefile
@@ -1,11 +1,10 @@
PORTNAME= pymtl
-DISTVERSION= 3.1.16
-PORTREVISION= 1
+DISTVERSIONPREFIX= v
+DISTVERSION= 3.1.17
CATEGORIES= cad python
-MASTER_SITES= PYPI
+#MASTER_SITES= PYPI # no tests
PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX}
PKGNAMESUFFIX= ${PORTVERSION:R:R}
-DISTNAME= ${PORTNAME}${PORTVERSION:R:R}-${DISTVERSION}
MAINTAINER= yuri@FreeBSD.org
COMMENT= Python-based hardware generation, simulation, verification framework
@@ -23,10 +22,17 @@ TEST_DEPENDS= ${PYTHON_PKGNAMEPREFIX}graphviz>0:graphics/py-graphviz@${PY_FLAVOR
yosys:cad/yosys
USES= python
-USE_PYTHON= autoplist distutils pytest # 94 tests fail, see https://github.com/pymtl/pymtl3/issues/247
+USE_PYTHON= autoplist distutils pytest
+
+USE_GITHUB= yes
+GH_ACCOUNT= pymtl
+GH_PROJECT= pymtl3
BINARY_ALIAS= g++=${CXX}
+TEST_ARGS= --disable-plugin-autoload -p pytest_plugin.pytest_pymtl3
NO_ARCH= yes
+# tests as of 3.1.17: 1934 passed, 20 xfailed, 62395 warnings in 5104.62s (1:25:04)
+
.include <bsd.port.mk>
diff --git a/cad/py-pymtl/distinfo b/cad/py-pymtl/distinfo
index 28d19dfd4dd0..dbceeefb17e5 100644
--- a/cad/py-pymtl/distinfo
+++ b/cad/py-pymtl/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1699065742
-SHA256 (pymtl3-3.1.16.tar.gz) = f0e1329c45fb8d42527714537ea734345dd69485b72fc3d22ef1d215a40b60f3
-SIZE (pymtl3-3.1.16.tar.gz) = 350199
+TIMESTAMP = 1789678579
+SHA256 (pymtl-pymtl3-v3.1.17_GH0.tar.gz) = 130b22773965862962f59fb4cdf547a431562ccde59521f0fbe85ccbd0c857d3
+SIZE (pymtl-pymtl3-v3.1.17_GH0.tar.gz) = 436361
diff --git a/cad/py-pymtl/files/patch-pymtl3_passes_backends_verilog_import___VerilogVerilatorImportConfigs.py b/cad/py-pymtl/files/patch-pymtl3_passes_backends_verilog_import___VerilogVerilatorImportConfigs.py
index d8aee4a4357f..d4d42073ff02 100644
--- a/cad/py-pymtl/files/patch-pymtl3_passes_backends_verilog_import___VerilogVerilatorImportConfigs.py
+++ b/cad/py-pymtl/files/patch-pymtl3_passes_backends_verilog_import___VerilogVerilatorImportConfigs.py
@@ -1,8 +1,33 @@
-- remove GCC compiler flags, because we use clang
+-- Update the Verilator import config for the current FreeBSD toolchain.
+-- Simplify unsupported GCC-only compiler flags for clang, suppress fatal
+-- Verilator 5 warnings that are non-fatal for the tests, and find/reorder
+-- generated support files the way modern Verilator emits them.
---- pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportConfigs.py.orig 2023-06-11 22:18:55 UTC
+--- pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportConfigs.py.orig 2026-07-02 20:56:13 UTC
+++ pymtl3/passes/backends/verilog/import_/VerilogVerilatorImportConfigs.py
-@@ -317,9 +317,11 @@ class VerilogVerilatorImportConfigs( BasePassConfigs )
+@@ -6,6 +6,7 @@ import copy
+ """Configuration of Verilator import pass."""
+
+ import copy
++import glob
+ import os
+ import subprocess
+ from textwrap import fill, indent
+@@ -68,11 +69,11 @@ class VerilogVerilatorImportConfigs( BasePassConfigs )
+ # False to disable the warnings, True to enable
+ "vl_W_lint" : True,
+ "vl_W_style" : True,
+- "vl_W_fatal" : True,
++ "vl_W_fatal" : False,
+
+ # Un-warn all warnings in the given list; [] to disable this option
+ # The given list should only include strings that appear in `Warnings`
+- "vl_Wno_list" : [ 'UNOPTFLAT', 'UNSIGNED', 'WIDTH' ],
++ "vl_Wno_list" : [ 'MULTIDRIVEN', 'UNOPTFLAT', 'UNSIGNED', 'WIDTH' ],
+
+ # Verilator misc options
+
+@@ -317,9 +318,11 @@ class VerilogVerilatorImportConfigs( BasePassConfigs )
# (7/9/2020): Use -O0 by default so that normally the tests are super fast and don't corrupt cffi,
# but when the user gives a "fast" flag, it uses -O1.
if s.fast:
@@ -16,3 +41,44 @@
if not s.is_default("c_flags"):
c_flags += f" {expand(s.c_flags)}"
+@@ -347,9 +350,9 @@ class VerilogVerilatorImportConfigs( BasePassConfigs )
+ #---------------------
+
+ def _create_vl_warning_cmd( s ):
+- lint = "" if s.is_default("vl_W_lint") else "--Wno-lint"
+- style = "" if s.is_default("vl_W_style") else "--Wno-style"
+- fatal = "" if s.is_default("vl_W_fatal") else "--Wno-fatal"
++ lint = "" if s.vl_W_lint else "--Wno-lint"
++ style = "" if s.vl_W_style else "--Wno-style"
++ fatal = "" if s.vl_W_fatal else "--Wno-fatal"
+ wno = " ".join(f"--Wno-{w}" for w in s.vl_Wno_list)
+ return " ".join(w for w in [lint, style, fatal, wno] if w)
+
+@@ -382,7 +385,10 @@ $PYMTL_VERILATOR_INCLUDE_DIR is set or `pkg-config` ha
+ def _get_c_src_files( s ):
+ top_module = s.translated_top_module
+ vl_mk_dir = s.vl_mk_dir
+- vl_class_mk = f"{vl_mk_dir}/V{top_module}_classes.mk"
++ vl_class_mks = sorted(glob.glob(f"{vl_mk_dir}/*_classes.mk"))
++ if not vl_class_mks:
++ raise FileNotFoundError(f"No Verilator classes makefile found in {vl_mk_dir}")
++ vl_class_mk = vl_class_mks[0]
+
+ # Add C wrapper
+ o0 = []
+@@ -391,13 +397,13 @@ $PYMTL_VERILATOR_INCLUDE_DIR is set or `pkg-config` ha
+ # Add files listed in class makefile
+ with open(vl_class_mk) as class_mk:
+ all_lines = class_mk.readlines()
++ o1 += s._get_srcs_from_vl_class_mk( all_lines, s.vl_include_dir, "VM_GLOBAL_FAST")
+ o1 += s._get_srcs_from_vl_class_mk( all_lines, vl_mk_dir, "VM_CLASSES_FAST")
+ o1 += s._get_srcs_from_vl_class_mk( all_lines, vl_mk_dir, "VM_SUPPORT_FAST")
+- o1 += s._get_srcs_from_vl_class_mk( all_lines, s.vl_include_dir, "VM_GLOBAL_FAST")
+
++ o0 += s._get_srcs_from_vl_class_mk( all_lines, s.vl_include_dir, "VM_GLOBAL_SLOW")
+ o0 += s._get_srcs_from_vl_class_mk( all_lines, vl_mk_dir, "VM_CLASSES_SLOW")
+ o0 += s._get_srcs_from_vl_class_mk( all_lines, vl_mk_dir, "VM_SUPPORT_SLOW")
+- o0 += s._get_srcs_from_vl_class_mk( all_lines, s.vl_include_dir, "VM_GLOBAL_SLOW")
+
+ with open(f"{top_module}_v__ALL_pickled.cpp", 'w') as out:
+