git: 373b3edfdbc1 - main - cad/iverilog: Update to 13.0

From: Kevin Bowling <kbowling_at_FreeBSD.org>
Date: Fri, 06 Mar 2026 18:21:35 UTC
The branch main has been updated by kbowling:

URL: https://cgit.FreeBSD.org/ports/commit/?id=373b3edfdbc11983304e69ef84cf7da20b478ea3

commit 373b3edfdbc11983304e69ef84cf7da20b478ea3
Author:     Kevin Bowling <kbowling@FreeBSD.org>
AuthorDate: 2026-03-06 18:21:03 +0000
Commit:     Kevin Bowling <kbowling@FreeBSD.org>
CommitDate: 2026-03-06 18:21:03 +0000

    cad/iverilog: Update to 13.0
---
 cad/iverilog/Makefile  | 9 +++++----
 cad/iverilog/distinfo  | 6 +++---
 cad/iverilog/pkg-plist | 2 --
 3 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 7a2961825e9a..e8a204a8a3ed 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -1,9 +1,6 @@
 PORTNAME=	iverilog
-DISTVERSION=	12.0
-PORTREVISION=	2
+PORTVERSION=	13.0
 CATEGORIES=	cad
-MASTER_SITES=	SF/${PORTNAME}/${PORTNAME}/${DISTVERSION}
-DISTNAME=	verilog-${DISTVERSION}
 
 MAINTAINER=	kbowling@FreeBSD.org
 COMMENT=	Verilog simulation and synthesis tool
@@ -15,6 +12,10 @@ BUILD_DEPENDS=	gperf:devel/gperf
 
 USES=		bison compiler:c++11-lang gmake readline
 
+USE_GITHUB=	yes
+GH_ACCOUNT=	steveicarus
+GH_TAGNAME=	v13_0
+
 GNU_CONFIGURE=	yes
 CONFIGURE_ARGS=	--disable-suffix
 
diff --git a/cad/iverilog/distinfo b/cad/iverilog/distinfo
index c94c3b27a23c..4580ed2facbb 100644
--- a/cad/iverilog/distinfo
+++ b/cad/iverilog/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1757814677
-SHA256 (verilog-12.0.tar.gz) = 03848551a9c5ec390fefcff1bbcca14765c7aa035ee85bc9cbcb0424e0149fd4
-SIZE (verilog-12.0.tar.gz) = 3334697
+TIMESTAMP = 1772820908
+SHA256 (steveicarus-iverilog-13.0-v13_0_GH0.tar.gz) = c897bbfa9848688982c6d5c30529fc29d68df0b9ff22ffa73bad89db73a7ce49
+SIZE (steveicarus-iverilog-13.0-v13_0_GH0.tar.gz) = 3215392
diff --git a/cad/iverilog/pkg-plist b/cad/iverilog/pkg-plist
index 3d44dc586cd6..59adfff3fe4f 100644
--- a/cad/iverilog/pkg-plist
+++ b/cad/iverilog/pkg-plist
@@ -10,7 +10,6 @@ include/iverilog/vpi_user.h
 lib/ivl/blif-s.conf
 lib/ivl/blif.conf
 lib/ivl/blif.tgt
-lib/ivl/cadpli.vpl
 lib/ivl/include/constants.vams
 lib/ivl/include/disciplines.vams
 lib/ivl/ivl
@@ -44,7 +43,6 @@ lib/ivl/vhdlpp
 lib/ivl/vvp-s.conf
 lib/ivl/vvp.conf
 lib/ivl/vvp.tgt
-lib/libveriuser.a
 lib/libvpi.a
 share/man/man1/iverilog.1.gz
 share/man/man1/iverilog-vpi.1.gz