git: f2a3aae778d7 - main - cad/verilator: Fix run-time by adding missing include

From: Yuri Victorovich <yuri_at_FreeBSD.org>
Date: Wed, 21 May 2025 15:21:00 UTC 
The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=f2a3aae778d7bf381f4e0d2e7e376c1137695430

commit f2a3aae778d7bf381f4e0d2e7e376c1137695430
Author:     Yuri Victorovich <yuri@FreeBSD.org>
AuthorDate: 2025-05-21 15:18:47 +0000
Commit:     Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2025-05-21 15:20:53 +0000

    cad/verilator: Fix run-time by adding missing include
    
    PR:             286973
    Reported by:    Joel Bodenmann
---
 cad/verilator/Makefile | 4 ++++
 cad/verilator/distinfo | 4 +++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index c6a636aaef67..e876a7ce4d5b 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,8 +1,12 @@
 PORTNAME=	verilator
 DISTVERSIONPREFIX=	v
 DISTVERSION=	5.036
+PORTREVISION=	1
 CATEGORIES=	cad
 
+PATCH_SITES=	https://github.com/${GH_ACCOUNT}/${PORTNAME}/commit/
+PATCHFILES=	d94ed785888614cd53379b9faf58dfbde8f06b6f.patch:-p1 # https://github.com/verilator/verilator/pull/6028
+
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	Synthesizable Verilog to C++ compiler
 WWW=		https://www.veripool.org/verilator/ \
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index c98c261f5699..b171502a4b75 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,3 +1,5 @@
-TIMESTAMP = 1745827619
+TIMESTAMP = 1747840694
 SHA256 (verilator-verilator-v5.036_GH0.tar.gz) = 4199964882d56cf6a19ce80c6a297ebe3b0c35ea81106cd4f722342594337c47
 SIZE (verilator-verilator-v5.036_GH0.tar.gz) = 35527368
+SHA256 (d94ed785888614cd53379b9faf58dfbde8f06b6f.patch) = 6b4c604ff4b08ad76431fb0cf11858c0313db04cd6e539db9a3fbad5a03f2784
+SIZE (d94ed785888614cd53379b9faf58dfbde8f06b6f.patch) = 972