git: e192a5b6b398 - main - cad/qflow: update 1.4.103 → 1.4.104

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From: Yuri Victorovich <yuri_at_FreeBSD.org>
Date: Sun, 10 Nov 2024 23:53:16 UTC
The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=e192a5b6b39820c50fb66f01ea2abab217c65597

commit e192a5b6b39820c50fb66f01ea2abab217c65597
Author:     Älven <alster@vinterdalen.se>
AuthorDate: 2024-11-10 23:52:38 +0000
Commit:     Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2024-11-10 23:53:12 +0000

    cad/qflow: update 1.4.103 → 1.4.104
    
    PR:     282679
---
 cad/qflow/Makefile  | 2 +-
 cad/qflow/distinfo  | 6 +++---
 cad/qflow/pkg-descr | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/cad/qflow/Makefile b/cad/qflow/Makefile
index 8e3af7e328a5..aca8ba23305b 100644
--- a/cad/qflow/Makefile
+++ b/cad/qflow/Makefile
@@ -1,5 +1,5 @@
 PORTNAME=	qflow
-DISTVERSION=	1.4.103
+DISTVERSION=	1.4.104
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
diff --git a/cad/qflow/distinfo b/cad/qflow/distinfo
index 451648c41b30..075274938a79 100644
--- a/cad/qflow/distinfo
+++ b/cad/qflow/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1714976162
-SHA256 (RTimothyEdwards-qflow-1.4.103_GH0.tar.gz) = 8d04b14c94ae57e41efa4cdaa014150f57cd2f4fdccd48fb8bc50bac3ce06bea
-SIZE (RTimothyEdwards-qflow-1.4.103_GH0.tar.gz) = 946044
+TIMESTAMP = 1731246856
+SHA256 (RTimothyEdwards-qflow-1.4.104_GH0.tar.gz) = 48297322780cc2552a49f662b245809e8cb5fb286aac4b43734c36ff75f83c21
+SIZE (RTimothyEdwards-qflow-1.4.104_GH0.tar.gz) = 946203
diff --git a/cad/qflow/pkg-descr b/cad/qflow/pkg-descr
index a655ef084658..807bd2b6e372 100644
--- a/cad/qflow/pkg-descr
+++ b/cad/qflow/pkg-descr
@@ -1,5 +1,5 @@
 A digital synthesis flow is a set of tools and methods used to turn a circuit
-design written in a high-level behavioral language like verilog or VHDL into a
+design written in a high-level behavioral language like Verilog or VHDL into a
 physical circuit, which can either be configuration code for an FPGA target like
 a Xilinx or Altera chip, or a layout in a specific fabrication process
 technology, that would become part of a fabricated circuit chip. Several digital