git: 7e4f2be40627 - main - cad/yosys-ghdl-plugin: Add new port

The branch main has been updated by fuz:

URL: https://cgit.FreeBSD.org/ports/commit/?id=7e4f2be406274cd8a33b558308812fe07f1cbfea

commit 7e4f2be406274cd8a33b558308812fe07f1cbfea
Author:     Nico Sonack <nsonack@herrhotzenplotz.de>
AuthorDate: 2023-10-01 17:10:29 +0000
Commit:     Robert Clausecker <fuz@FreeBSD.org>
CommitDate: 2023-10-19 07:07:29 +0000

    cad/yosys-ghdl-plugin: Add new port
    
    This allows performing synthesis of VHDL using ghdl with yosys.
    
    Signed-off-by:  Nico Sonack <nsonack@herrhotzenplotz.de>
    PR:             274243
---
 cad/Makefile                    |  1 +
 cad/yosys-ghdl-plugin/Makefile  | 32 ++++++++++++++++++++++++++++++++
 cad/yosys-ghdl-plugin/distinfo  |  3 +++
 cad/yosys-ghdl-plugin/pkg-descr |  2 ++
 4 files changed, 38 insertions(+)

diff --git a/cad/Makefile b/cad/Makefile
index 2d54cd764cde..84e61e892167 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -153,6 +153,7 @@
     SUBDIR += xcircuit
     SUBDIR += xyce
     SUBDIR += yosys
+    SUBDIR += yosys-ghdl-plugin
     SUBDIR += yosys-systemverilog
     SUBDIR += z88
     SUBDIR += zcad
diff --git a/cad/yosys-ghdl-plugin/Makefile b/cad/yosys-ghdl-plugin/Makefile
new file mode 100644
index 000000000000..315bdec37b8e
--- /dev/null
+++ b/cad/yosys-ghdl-plugin/Makefile
@@ -0,0 +1,32 @@
+PORTNAME=	yosys-ghdl-plugin
+PORTVERSION=	g20230930
+CATEGORIES=	cad
+
+MAINTAINER=	nsonack@outlook.com
+COMMENT=	GHDL synthesis plugin for yosys
+WWW=		https://github.com/ghdl/ghdl-yosys-plugin
+
+LICENSE=	GPLv3
+
+BUILD_DEPENDS=	ghdl>0:cad/ghdl \
+		yosys>0:cad/yosys
+RUN_DEPENDS=	yosys>0:cad/yosys
+LIB_DEPENDS=	libffi.so:devel/libffi \
+		libghdl-3_0_0.so:cad/ghdl \
+		libtcmalloc.so:devel/google-perftools
+
+USES=		gmake readline tcl
+USE_GITHUB=	yes
+GH_ACCOUNT=	ghdl
+GH_PROJECT=	ghdl-yosys-plugin
+GH_TAGNAME=	d44a7bccdaa458ab3ec0ce83459410604bee6c60
+
+MAKE_ENV+=	GHDL=${LOCALBASE}/bin/ghdl \
+		YOSYS_CONFIG=${LOCALBASE}/bin/yosys-config
+
+PLIST_FILES=	share/yosys/plugins/ghdl.so
+
+post-install:
+	${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/ghdl.so
+
+.include <bsd.port.mk>
diff --git a/cad/yosys-ghdl-plugin/distinfo b/cad/yosys-ghdl-plugin/distinfo
new file mode 100644
index 000000000000..28580a99a0bb
--- /dev/null
+++ b/cad/yosys-ghdl-plugin/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1696080191
+SHA256 (ghdl-ghdl-yosys-plugin-g20230930-d44a7bccdaa458ab3ec0ce83459410604bee6c60_GH0.tar.gz) = 200f38ea69d868b111a905d95a59aefa0c24d42f4f092ed5e5d94db21c496643
+SIZE (ghdl-ghdl-yosys-plugin-g20230930-d44a7bccdaa458ab3ec0ce83459410604bee6c60_GH0.tar.gz) = 82663
diff --git a/cad/yosys-ghdl-plugin/pkg-descr b/cad/yosys-ghdl-plugin/pkg-descr
new file mode 100644
index 000000000000..ff7a7160bc63
--- /dev/null
+++ b/cad/yosys-ghdl-plugin/pkg-descr
@@ -0,0 +1,2 @@
+yosys-ghdl-plugin is a plugin that enables synthesis of VHDL with
+yosys and ghdl.