git: e1f76ec54d34 - main - cad/cvc: New port: Circuit Validity Checker
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Date: Wed, 29 Dec 2021 07:37:22 UTC
The branch main has been updated by yuri:
URL: https://cgit.FreeBSD.org/ports/commit/?id=e1f76ec54d34af17e2db4acad7a3bd29645dcef6
commit e1f76ec54d34af17e2db4acad7a3bd29645dcef6
Author: Yuri Victorovich <yuri@FreeBSD.org>
AuthorDate: 2021-12-29 07:33:10 +0000
Commit: Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2021-12-29 07:37:20 +0000
cad/cvc: New port: Circuit Validity Checker
---
cad/Makefile | 1 +
cad/cvc/Makefile | 32 ++++++++++++++++++++++++++++
cad/cvc/distinfo | 3 +++
cad/cvc/files/patch-Makefile.am | 10 +++++++++
cad/cvc/files/patch-src_Makefile.am | 11 ++++++++++
cad/cvc/files/patch-src_mmap__file__pool.cpp | 15 +++++++++++++
cad/cvc/files/patch-src_obstack.c | 11 ++++++++++
cad/cvc/pkg-descr | 16 ++++++++++++++
cad/cvc/pkg-plist | 11 ++++++++++
9 files changed, 110 insertions(+)
diff --git a/cad/Makefile b/cad/Makefile
index 17bfa30c6f12..219f0338d970 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -22,6 +22,7 @@
SUBDIR += csxcad
SUBDIR += cura
SUBDIR += cura-engine
+ SUBDIR += cvc
SUBDIR += digital
SUBDIR += dinotrace
SUBDIR += ecpprog
diff --git a/cad/cvc/Makefile b/cad/cvc/Makefile
new file mode 100644
index 000000000000..84b75a2d1bb0
--- /dev/null
+++ b/cad/cvc/Makefile
@@ -0,0 +1,32 @@
+PORTNAME= cvc
+DISTVERSIONPREFIX= v
+DISTVERSION= 1.1.0-4
+DISTVERSIONSUFFIX= -gd172016
+CATEGORIES= cad
+
+MAINTAINER= yuri@FreeBSD.org
+COMMENT= Circuit Validity Checker
+
+LICENSE= GPLv3
+LICENSE_FILE= ${WRKSRC}/LICENSE
+
+BUILD_DEPENDS= pyinstaller:devel/py-pyinstaller@${PY_FLAVOR} \
+ bash:shells/bash
+
+USES= autoreconf bison gettext-runtime gettext-tools gmake python readline shebangfix
+USE_GCC= yes # clang fails, see https://github.com/d-m-bailey/cvc/issues/239
+
+SHEBANG_FILES= scripts/calibre_cvc scripts/clean_cvc_log scripts/expand_cells.py
+
+GNU_CONFIGURE= yes
+
+USE_GITHUB= yes
+GH_ACCOUNT= d-m-bailey
+
+MAKE_ARGS= INTLLIBS=-lintl
+
+OPTIONS_DEFINE= DOCS
+
+PORTDOCS= *
+
+.include <bsd.port.mk>
diff --git a/cad/cvc/distinfo b/cad/cvc/distinfo
new file mode 100644
index 000000000000..60badc1f5ea0
--- /dev/null
+++ b/cad/cvc/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1640757467
+SHA256 (d-m-bailey-cvc-v1.1.0-4-gd172016_GH0.tar.gz) = d09725c54079911fb4844d0df17d053b3657de6acf5a1cc187f7bd3b619a5178
+SIZE (d-m-bailey-cvc-v1.1.0-4-gd172016_GH0.tar.gz) = 328311
diff --git a/cad/cvc/files/patch-Makefile.am b/cad/cvc/files/patch-Makefile.am
new file mode 100644
index 000000000000..c5fdd5a1f1b5
--- /dev/null
+++ b/cad/cvc/files/patch-Makefile.am
@@ -0,0 +1,10 @@
+--- Makefile.am.orig 2021-12-29 02:03:06 UTC
++++ Makefile.am
+@@ -1,6 +1,6 @@
+ AUTOMAKE_OPTIONS = foreign
+ #SUBDIRS = po src
+-SUBDIRS = src scripts src_py doc
++SUBDIRS = src scripts doc
+
+ ACLOCAL_AMFLAGS = -I m4
+
diff --git a/cad/cvc/files/patch-src_Makefile.am b/cad/cvc/files/patch-src_Makefile.am
new file mode 100644
index 000000000000..d07dbacaf66b
--- /dev/null
+++ b/cad/cvc/files/patch-src_Makefile.am
@@ -0,0 +1,11 @@
+--- src/Makefile.am.orig 2021-12-29 05:59:48 UTC
++++ src/Makefile.am
+@@ -1,6 +1,6 @@
+ # what flags you want to pass to the C compiler & linker
+-CFLAGS = -O3
+-CXXFLAGS = -O3 -std=gnu++11
++#CFLAGS = -O3
++CXXFLAGS += -std=gnu++11
+ #LIBS = -lz -lreadline -lcurses -lhistory -lintl
+ LIBS = -lz -lreadline -lcurses -lhistory $(INTLLIBS)
+ LDFLAGS = -static-libstdc++ -static-libgcc
diff --git a/cad/cvc/files/patch-src_mmap__file__pool.cpp b/cad/cvc/files/patch-src_mmap__file__pool.cpp
new file mode 100644
index 000000000000..8718ccdeb8d3
--- /dev/null
+++ b/cad/cvc/files/patch-src_mmap__file__pool.cpp
@@ -0,0 +1,15 @@
+--- src/mmap_file_pool.cpp.orig 2021-12-28 19:09:39 UTC
++++ src/mmap_file_pool.cpp
+@@ -116,7 +116,12 @@ namespace mmap_allocator_namespace {
+ throw mmap_allocator_exception("Error in remmap(fd)");
+
+ void *last_address = memory_area;
++#if defined(__FreeBSD__)
++ memory_area = mmap(last_address, size_mapped, PROT_READ, MAP_SHARED, fd, 0);
++#else
+ memory_area = mmap(last_address, size_mapped, PROT_READ, MAP_SHARED | MAP_NORESERVE, fd, 0);
++#endif
++
+ if (memory_area == MAP_FAILED) {
+ if (get_verbosity() > 0) {
+ perror("mmap");
diff --git a/cad/cvc/files/patch-src_obstack.c b/cad/cvc/files/patch-src_obstack.c
new file mode 100644
index 000000000000..313ba177999f
--- /dev/null
+++ b/cad/cvc/files/patch-src_obstack.c
@@ -0,0 +1,11 @@
+--- src/obstack.c.orig 2021-12-28 19:08:19 UTC
++++ src/obstack.c
+@@ -29,7 +29,7 @@
+ # include "obstack.h"
+ #endif
+
+-#include <stdint-gcc.h>
++//#include <stdint-gcc.h>
+
+ /* NOTE BEFORE MODIFYING THIS FILE: This version number must be
+ incremented whenever callers compiled using an old obstack.h can no
diff --git a/cad/cvc/pkg-descr b/cad/cvc/pkg-descr
new file mode 100644
index 000000000000..2efbc4aeb4df
--- /dev/null
+++ b/cad/cvc/pkg-descr
@@ -0,0 +1,16 @@
+CVC: Circuit Validity Checker. Voltage aware ERC checker for CDL netlists.
+
+Features:
+* Input netlist format is Calibre LVS CDL (Mentor, a Siemens business)
+* Checks netlists with up to 4B devices (2^32).
+* Power and device parameters from Microsoft Excel
+* Hierarchical power files possible
+* Ability to differentiate models by parameters
+* Setup option to list models and power nets
+* All rules are automated. No need to write rule files.
+* Interactive netlist analyzer
+* Script execution available
+* Automatic subcircuit debug environment creation
+* GUI to record error analyses results
+
+WWW: https://github.com/d-m-bailey/cvc
diff --git a/cad/cvc/pkg-plist b/cad/cvc/pkg-plist
new file mode 100644
index 000000000000..917be4f6980f
--- /dev/null
+++ b/cad/cvc/pkg-plist
@@ -0,0 +1,11 @@
+bin/add_kisei
+bin/annotate_kisei
+bin/calibre_cvc
+bin/clean_cvc_log
+bin/cvc
+bin/cvcMakefile
+bin/cvc_probe.il
+bin/cvc_select.tcl
+bin/expand_cells.py
+share/scripts/cvc/SaveCvcParameters.txt
+share/scripts/cvc/box.awk