git: 0c3b0438610d - main - cad/py-verilog-parser: [NEW PORT] Lark-based parser for structural Verilog netlists

The branch main has been updated by alven:

URL: https://cgit.FreeBSD.org/ports/commit/?id=0c3b0438610d15b209b235f038d6fc450d30ef27

commit 0c3b0438610d15b209b235f038d6fc450d30ef27
Author:     Aryan Karamtoth <spaciouscoder78@disroot.org>
AuthorDate: 2025-10-20 03:00:05 +0000
Commit:     Älven <alven@FreeBSD.org>
CommitDate: 2025-10-30 18:06:51 +0000

    cad/py-verilog-parser: [NEW PORT] Lark-based parser for structural Verilog netlists
    
    PR:             290373
    Approved by:    yuri@ (Mentor)
---
 cad/Makefile                    |  1 +
 cad/py-verilog-parser/Makefile  | 22 ++++++++++++++++++++++
 cad/py-verilog-parser/distinfo  |  3 +++
 cad/py-verilog-parser/pkg-descr |  3 +++
 4 files changed, 29 insertions(+)

diff --git a/cad/Makefile b/cad/Makefile
index ec2dc7d8acfa..5ff61f95df60 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -119,6 +119,7 @@
     SUBDIR += py-pygmsh
     SUBDIR += py-pymtl
     SUBDIR += py-pyvcd
+    SUBDIR += py-verilog-parser
     SUBDIR += py-vunit-hdl
     SUBDIR += python-gdsii
     SUBDIR += qcad
diff --git a/cad/py-verilog-parser/Makefile b/cad/py-verilog-parser/Makefile
new file mode 100644
index 000000000000..fc80dfa1d142
--- /dev/null
+++ b/cad/py-verilog-parser/Makefile
@@ -0,0 +1,22 @@
+PORTNAME=	verilog_parser
+DISTVERSION=	0.0.7
+CATEGORIES=	cad python
+MASTER_SITES=	PYPI
+PKGNAMEPREFIX=	${PYTHON_PKGNAMEPREFIX}
+
+MAINTAINER=	spaciouscoder78@disroot.org
+COMMENT=	Lark-based parser for structural Verilog netlists
+WWW=		https://codeberg.org/tok/py-verilog-parser
+
+LICENSE=	AGPLv3+
+
+BUILD_DEPENDS=	${PY_SETUPTOOLS} \
+		${PYTHON_PKGNAMEPREFIX}lark>=1.2.2<2:devel/py-lark@${PY_FLAVOR} \
+		${PYTHON_PKGNAMEPREFIX}wheel>=0.45.1:devel/py-wheel@${PY_FLAVOR}
+
+USES=		python
+USE_PYTHON=	autoplist pep517
+
+NO_ARCH=	yes
+
+.include <bsd.port.mk>
diff --git a/cad/py-verilog-parser/distinfo b/cad/py-verilog-parser/distinfo
new file mode 100644
index 000000000000..7a375cc4cb10
--- /dev/null
+++ b/cad/py-verilog-parser/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1760924808
+SHA256 (verilog_parser-0.0.7.tar.gz) = dbe6db18bc74398fa481ca373205818065cac2ac0e165886ce373b01bdf8e0f7
+SIZE (verilog_parser-0.0.7.tar.gz) = 7197
diff --git a/cad/py-verilog-parser/pkg-descr b/cad/py-verilog-parser/pkg-descr
new file mode 100644
index 000000000000..24ea3cd3d8fb
--- /dev/null
+++ b/cad/py-verilog-parser/pkg-descr
@@ -0,0 +1,3 @@
+Lark-based parser for Verilog netlists (structural Verilog without behavioral
+statements). This is meant to be used to read netlists as generated by HDL logic
+synthesizers such as Yosys.