git: 5d7b36799123 - main - cad/verilator: Update 5.040 => 5.042, unbreak on i386

From: Älven <alven_at_FreeBSD.org>
Date: Mon, 03 Nov 2025 12:49:02 UTC
The branch main has been updated by alven:

URL: https://cgit.FreeBSD.org/ports/commit/?id=5d7b367991236009d5c3ab96941a3314636cc361

commit 5d7b367991236009d5c3ab96941a3314636cc361
Author:     Älven <alven@FreeBSD.org>
AuthorDate: 2025-11-03 01:56:11 +0000
Commit:     Älven <alven@FreeBSD.org>
CommitDate: 2025-11-03 12:48:36 +0000

    cad/verilator: Update 5.040 => 5.042, unbreak on i386
    
    Changelogs:
    * https://github.com/verilator/verilator/releases/tag/v5.042
    * https://github.com/verilator/verilator/compare/v5.040...v5.042
    
    * Clarify LICENSE
    
    Approved by:            yuri@ (maintainer, Mentor)
    Differential Revision:  https://reviews.freebsd.org/D53544
---
 cad/verilator/Makefile                             | 10 +++++-----
 cad/verilator/distinfo                             |  6 +++---
 cad/verilator/files/patch-include_verilatedos__c.h | 14 ++++++++++++++
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index 33b25b4bc57d..e382744618b2 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,6 +1,6 @@
 PORTNAME=	verilator
 DISTVERSIONPREFIX=	v
-DISTVERSION=	5.040
+DISTVERSION=	5.042
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
@@ -8,10 +8,10 @@ COMMENT=	Synthesizable Verilog to C++ compiler
 WWW=		https://www.veripool.org/verilator/ \
 		https://github.com/verilator/verilator
 
-LICENSE=	GPLv3
-LICENSE_FILE=	${WRKSRC}/LICENSE
-
-BROKEN_i386=	see https://github.com/verilator/verilator/issues/3037
+LICENSE=	ART20 LGPL3+
+LICENSE_COMB=	dual
+LICENSE_FILE_ART20=	${WRKSRC}/Artistic
+LICENSE_FILE_LGPL3+ =	${WRKSRC}/LICENSE
 
 BUILD_DEPENDS=	${LOCALBASE}/bin/ar:devel/binutils \
 		autoconf>0:devel/autoconf \
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index 0f3c2aa6244c..c014c9e5dcb5 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1759278141
-SHA256 (verilator-verilator-v5.040_GH0.tar.gz) = 56c7c46314adfad06dd093b77823bfd9b49ebef72342549f790718199c3e8223
-SIZE (verilator-verilator-v5.040_GH0.tar.gz) = 35762924
+TIMESTAMP = 1762132333
+SHA256 (verilator-verilator-v5.042_GH0.tar.gz) = bec14f17de724851b110b698f3bd25e22effaaced7265b26d2bc13075dbfb4bf
+SIZE (verilator-verilator-v5.042_GH0.tar.gz) = 4670033
diff --git a/cad/verilator/files/patch-include_verilatedos__c.h b/cad/verilator/files/patch-include_verilatedos__c.h
new file mode 100644
index 000000000000..81983a1e9229
--- /dev/null
+++ b/cad/verilator/files/patch-include_verilatedos__c.h
@@ -0,0 +1,14 @@
+--- include/verilatedos_c.h.orig	2025-11-02 16:12:46 UTC
++++ include/verilatedos_c.h
+@@ -41,6 +41,11 @@
+ #if defined(__APPLE__) && !defined(__arm64__) && !defined(__POWERPC__)
+ # include <cpuid.h>  // For __cpuid_count()
+ #endif
++
++#ifdef __FreeBSD__
++#include <pthread_np.h>
++#endif
++
+ // clang-format on
+ 
+ namespace VlOs {