git: 3a3bceadc7f3 - main - cad/yosys-systemverilog: Broken

From: Yuri Victorovich <yuri_at_FreeBSD.org>
Date: Sat, 29 Jul 2023 06:39:36 UTC 
The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4

commit 3a3bceadc7f3a2cd6ff0848ff93bfa57da3f98e4
Author:     Yuri Victorovich <yuri@FreeBSD.org>
AuthorDate: 2023-07-29 06:39:15 +0000
Commit:     Yuri Victorovich <yuri@FreeBSD.org>
CommitDate: 2023-07-29 06:39:15 +0000

    cad/yosys-systemverilog: Broken
    
    Reported by:    fallout
---
 cad/yosys-systemverilog/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cad/yosys-systemverilog/Makefile b/cad/yosys-systemverilog/Makefile
index 8918269008c0..f7b6e2d8c631 100644
--- a/cad/yosys-systemverilog/Makefile
+++ b/cad/yosys-systemverilog/Makefile
@@ -10,6 +10,8 @@ WWW=		https://github.com/antmicro/yosys-systemverilog
 LICENSE=	APACHE20
 LICENSE_FILE=	${WRKSRC}/LICENSE
 
+BROKEN=		incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845
+
 BUILD_DEPENDS=	bash:shells/bash \
 		yosys>0:cad/yosys
 LIB_DEPENDS=	libcapnp.so:devel/capnproto \