git: e9dbdb0bf8 - main - splitlocks 2026q3 status report

The branch main has been updated by kib:

URL: https://cgit.FreeBSD.org/doc/commit/?id=e9dbdb0bf8950c1a85599392c3631f6344830d09

commit e9dbdb0bf8950c1a85599392c3631f6344830d09
Author:     Konstantin Belousov <kib@FreeBSD.org>
AuthorDate: 2026-10-03 03:01:25 +0000
Commit:     Konstantin Belousov <kib@FreeBSD.org>
CommitDate: 2026-10-16 14:10:13 +0000

    splitlocks 2026q3 status report
    
    Reviewed by:    salvadore
    Sponsored by:   The FreeBSD Foundation
    Differential revision:  https://reviews.freebsd.org/D60272
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 .../status/report-2026-07-2026-09/splitlocks.adoc  | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/website/content/en/status/report-2026-07-2026-09/splitlocks.adoc b/website/content/en/status/report-2026-07-2026-09/splitlocks.adoc
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+=== x86 splitlocks detection support
+
+Contact: Konstantin Belousov <kib@FreeBSD.org>
+
+Most non-x86 platforms are relatively strict with regard to the proper alignment of the data types.
+On the other hand, x86 ISA allows any alignment for the operands of integer scalar operations.
+
+Still, there is an AC control bit in the processor flags register which causes alignment exception (fault) on unaligned operations.
+Practically the bit is not too useful because most of the compilers generate code that relies on the freedom of the working unaligned access on x86.
+
+Particularly interesting case of the unaligned access is when the disposition of the operand causes it to span two cache lines (which is impossible for naturally aligned data).
+Normal (unlocked) operations cause so called torn reads and writes.
+This effect become observable starting with Core2 Intel microarchitecture.
+
+Even more interesting case is provided by the locked operations using the LOCK prefix on read-modify-write instruction with the mis-aligned data.
+To satisfy ISA guarantees in this case, the CPU has to either take more than one cache line for exclusive ownership in MESI-like cache coherence protocol, or exercise so called bus lock ensuring global cache ownership.
+Either option has very high cost and causes observable detrimental effects on other processes and virtual machines executing on the same physical host.
+
+Since some time Intel provides a control for the lock operations that need to span more than one cache line (split locks).
+Turning the control on causes split locks to generate the same #AC exception as done by the AC flag, but only for the split locks, instead of all unaligned accesses.
+
+The feature is controlled by the platform MSR and is per-CPU global, which precludes making the MSR directly available to userspace.
+The new man:sysarch[2] operation I386_SET_SPLITLOCK was developed that enables the control for the calling thread.
+The control is part of the machine state maintained on the context switch.
+
+The intent is mainly to assist in catching bugs where improperly alignment locking structures are created, unlike Linux, which uses the feature to artificially penalize such processes by slowing them down.
+If the program code modifications are not possible, users and administrators can LD_PRELOAD a trivial shared object that turns the control on.
+
+Sponsor: The FreeBSD Foundation