svn commit: r206954 - user/jmallett/octeon/contrib/gcc/config/mips
Juli Mallett
jmallett at FreeBSD.org
Tue Apr 20 23:35:20 UTC 2010
Author: jmallett
Date: Tue Apr 20 23:35:20 2010
New Revision: 206954
URL: http://svn.freebsd.org/changeset/base/206954
Log:
Teach our GCC a little bit about mips64r2. This is enough to compile code
from the Cavium SDK which needs the assembler in mips64r2, which our BU
supports well enough for basic things.
Modified:
user/jmallett/octeon/contrib/gcc/config/mips/freebsd.h
user/jmallett/octeon/contrib/gcc/config/mips/mips.c
user/jmallett/octeon/contrib/gcc/config/mips/mips.h
user/jmallett/octeon/contrib/gcc/config/mips/mips.md
Modified: user/jmallett/octeon/contrib/gcc/config/mips/freebsd.h
==============================================================================
--- user/jmallett/octeon/contrib/gcc/config/mips/freebsd.h Tue Apr 20 22:59:56 2010 (r206953)
+++ user/jmallett/octeon/contrib/gcc/config/mips/freebsd.h Tue Apr 20 23:35:20 2010 (r206954)
@@ -231,13 +231,13 @@ Boston, MA 02110-1301, USA. */
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
builtin_define ("__mips_isa_rev=1"); \
} \
-/* else if (ISA_MIPS64R2) \
+ else if (ISA_MIPS64R2) \
{ \
builtin_define ("__mips=64"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
builtin_define ("__mips_isa_rev=2"); \
} \
-*/ \
+ \
if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
Modified: user/jmallett/octeon/contrib/gcc/config/mips/mips.c
==============================================================================
--- user/jmallett/octeon/contrib/gcc/config/mips/mips.c Tue Apr 20 22:59:56 2010 (r206953)
+++ user/jmallett/octeon/contrib/gcc/config/mips/mips.c Tue Apr 20 23:35:20 2010 (r206954)
@@ -713,6 +713,7 @@ const struct mips_cpu_info mips_cpu_info
{ "mips32", PROCESSOR_4KC, 32 },
{ "mips32r2", PROCESSOR_M4K, 33 },
{ "mips64", PROCESSOR_5KC, 64 },
+ { "mips64r2", PROCESSOR_5KC, 65 },
/* MIPS I */
{ "r3000", PROCESSOR_R3000, 1 },
@@ -4829,7 +4830,7 @@ override_options (void)
issue those instructions unless instructed to do so by
-mbranch-likely. */
if (ISA_HAS_BRANCHLIKELY
- && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
+ && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
&& !(TUNE_MIPS5500 || TUNE_SB1))
target_flags |= MASK_BRANCHLIKELY;
else
Modified: user/jmallett/octeon/contrib/gcc/config/mips/mips.h
==============================================================================
--- user/jmallett/octeon/contrib/gcc/config/mips/mips.h Tue Apr 20 22:59:56 2010 (r206953)
+++ user/jmallett/octeon/contrib/gcc/config/mips/mips.h Tue Apr 20 23:35:20 2010 (r206954)
@@ -199,6 +199,7 @@ extern const struct mips_rtx_cost_data *
#define ISA_MIPS32 (mips_isa == 32)
#define ISA_MIPS32R2 (mips_isa == 33)
#define ISA_MIPS64 (mips_isa == 64)
+#define ISA_MIPS64R2 (mips_isa == 65)
/* Architecture target defines. */
#define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
@@ -380,6 +381,12 @@ extern const struct mips_rtx_cost_data *
builtin_define ("__mips_isa_rev=1"); \
builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
} \
+ else if (ISA_MIPS64R2) \
+ { \
+ builtin_define ("__mips=64"); \
+ builtin_define ("__mips_isa_rev=2"); \
+ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
+ } \
\
if (TARGET_HARD_FLOAT) \
builtin_define ("__mips_hard_float"); \
@@ -501,7 +508,11 @@ extern const struct mips_rtx_cost_data *
# if MIPS_ISA_DEFAULT == 64
# define MULTILIB_ISA_DEFAULT "mips64"
# else
-# define MULTILIB_ISA_DEFAULT "mips1"
+# if MIPS_ISA_DEFAULT == 65
+# define MULTILIB_ISA_DEFAULT "mips64r2"
+# else
+# define MULTILIB_ISA_DEFAULT "mips1"
+# endif
# endif
# endif
# endif
@@ -562,7 +573,8 @@ extern const struct mips_rtx_cost_data *
|| TARGET_MAD \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* Generate three-operand multiply instructions for DImode. */
@@ -584,7 +596,8 @@ extern const struct mips_rtx_cost_data *
/* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
#define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
|| ISA_MIPS4 \
- || ISA_MIPS64)
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2)
/* ISA has branch likely instructions (e.g. mips2). */
/* Disable branchlikely for tx39 until compare rewrite. They haven't
@@ -595,7 +608,8 @@ extern const struct mips_rtx_cost_data *
#define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
&& !TARGET_MIPS5500 \
&& !TARGET_MIPS16)
@@ -604,13 +618,15 @@ extern const struct mips_rtx_cost_data *
#define ISA_HAS_8CC (ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
- || ISA_MIPS64)
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2)
/* This is a catch all for other mips4 instructions: indexed load, the
FP madd and msub instructions, and the FP recip and recip sqrt
instructions. */
#define ISA_HAS_FP4 ((ISA_MIPS4 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* ISA has conditional trap instructions. */
@@ -621,11 +637,13 @@ extern const struct mips_rtx_cost_data *
#define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
+ || ISA_MIPS64R2 \
) && !TARGET_MIPS16)
/* ISA has floating-point nmadd and nmsub instructions. */
#define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
&& (!TARGET_MIPS5400 || TARGET_MAD) \
&& ! TARGET_MIPS16)
@@ -633,11 +651,13 @@ extern const struct mips_rtx_cost_data *
#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
+ || ISA_MIPS64R2 \
) && !TARGET_MIPS16)
/* ISA has double-word count leading zeroes/ones instruction (not
implemented). */
#define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
+ || ISA_MIPS64R2 \
&& !TARGET_MIPS16)
/* ISA has three operand multiply instructions that put
@@ -677,6 +697,7 @@ extern const struct mips_rtx_cost_data *
/* ISA has 32-bit rotate right instruction. */
#define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || ISA_MIPS64R2 \
|| TARGET_MIPS5400 \
|| TARGET_MIPS5500 \
|| TARGET_SR71K \
@@ -694,7 +715,8 @@ extern const struct mips_rtx_cost_data *
#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* ISA has data indexed prefetch instructions. This controls use of
@@ -702,7 +724,8 @@ extern const struct mips_rtx_cost_data *
(prefx is a cop1x instruction, so can only be used if FP is
enabled.) */
#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
- || ISA_MIPS64) \
+ || ISA_MIPS64 \
+ || ISA_MIPS64R2) \
&& !TARGET_MIPS16)
/* True if trunc.w.s and trunc.w.d are real (not synthetic)
@@ -713,11 +736,13 @@ extern const struct mips_rtx_cost_data *
/* ISA includes the MIPS32r2 seb and seh instructions. */
#define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || ISA_MIPS64R2 \
))
/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
#define ISA_HAS_EXT_INS (!TARGET_MIPS16 \
&& (ISA_MIPS32R2 \
+ || ISA_MIPS64R2 \
))
/* True if the result of a load is not available to the next instruction.
@@ -748,6 +773,7 @@ extern const struct mips_rtx_cost_data *
#define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64 \
+ || ISA_MIPS64R2 \
|| TARGET_MIPS5500)
/* Add -G xx support. */
Modified: user/jmallett/octeon/contrib/gcc/config/mips/mips.md
==============================================================================
--- user/jmallett/octeon/contrib/gcc/config/mips/mips.md Tue Apr 20 22:59:56 2010 (r206953)
+++ user/jmallett/octeon/contrib/gcc/config/mips/mips.md Tue Apr 20 23:35:20 2010 (r206954)
@@ -1041,7 +1041,8 @@
|| TARGET_MIPS9000
|| ISA_MIPS32
|| ISA_MIPS32R2
- || ISA_MIPS64)
+ || ISA_MIPS64
+ || ISA_MIPS64R2)
return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2";
}
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