svn commit: r211382 - stable/7/sys/dev/bce
Pyun YongHyeon
yongari at FreeBSD.org
Sun Aug 15 23:32:24 UTC 2010
Author: yongari
Date: Sun Aug 15 23:32:23 2010
New Revision: 211382
URL: http://svn.freebsd.org/changeset/base/211382
Log:
MFC r207411:
- Enable flow control.
- Print device details only when verbose boot is enabled.
- Add debug output for shared memory access.
- Add debug statistics (checksum offload & VLAN frame counters).
- Modify TX path to update consumer index for each frame completed
rather than updating the consumer index only once for a group of
frames to improve small packet performance.
- Print driver/firmware pulse messages only when verbose boot
is enabled.
- Add debug sysctl to clear statistics.
- Fix more style(9) violations.
Modified:
stable/7/sys/dev/bce/if_bce.c
stable/7/sys/dev/bce/if_bcereg.h
Directory Properties:
stable/7/sys/ (props changed)
stable/7/sys/cddl/contrib/opensolaris/ (props changed)
stable/7/sys/contrib/dev/acpica/ (props changed)
stable/7/sys/contrib/pf/ (props changed)
Modified: stable/7/sys/dev/bce/if_bce.c
==============================================================================
--- stable/7/sys/dev/bce/if_bce.c Sun Aug 15 23:30:53 2010 (r211381)
+++ stable/7/sys/dev/bce/if_bce.c Sun Aug 15 23:32:23 2010 (r211382)
@@ -303,7 +303,7 @@ static void bce_dump_txbd (struct bce_s
static void bce_dump_rxbd (struct bce_softc *,
int, struct rx_bd *);
#ifdef BCE_JUMBO_HDRSPLIT
-static void bce_dump_pgbd (struct bce_softc *,
+static void bce_dump_pgbd (struct bce_softc *,
int, struct rx_bd *);
#endif
static void bce_dump_l2fhdr (struct bce_softc *,
@@ -368,7 +368,7 @@ static int bce_nvram_write (struct bce
/****************************************************************************/
static void bce_get_media (struct bce_softc *);
static void bce_init_media (struct bce_softc *);
-static void bce_dma_map_addr (void *,
+static void bce_dma_map_addr (void *,
bus_dma_segment_t *, int, int);
static int bce_dma_alloc (device_t);
static void bce_dma_free (struct bce_softc *);
@@ -379,7 +379,7 @@ static void bce_release_resources (struc
/****************************************************************************/
static int bce_fw_sync (struct bce_softc *, u32);
static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32);
-static void bce_load_cpu_fw (struct bce_softc *,
+static void bce_load_cpu_fw (struct bce_softc *,
struct cpu_reg *, struct fw_info *);
static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
@@ -401,21 +401,21 @@ static int bce_blockinit (struct bce_
static int bce_init_tx_chain (struct bce_softc *);
static void bce_free_tx_chain (struct bce_softc *);
-static int bce_get_rx_buf (struct bce_softc *,
+static int bce_get_rx_buf (struct bce_softc *,
struct mbuf *, u16 *, u16 *, u32 *);
static int bce_init_rx_chain (struct bce_softc *);
static void bce_fill_rx_chain (struct bce_softc *);
static void bce_free_rx_chain (struct bce_softc *);
#ifdef BCE_JUMBO_HDRSPLIT
-static int bce_get_pg_buf (struct bce_softc *,
+static int bce_get_pg_buf (struct bce_softc *,
struct mbuf *, u16 *, u16 *);
static int bce_init_pg_chain (struct bce_softc *);
static void bce_fill_pg_chain (struct bce_softc *);
static void bce_free_pg_chain (struct bce_softc *);
#endif
-static struct mbuf *bce_tso_setup (struct bce_softc *,
+static struct mbuf *bce_tso_setup (struct bce_softc *,
struct mbuf **, u16 *);
static int bce_tx_encap (struct bce_softc *, struct mbuf **);
static void bce_start_locked (struct ifnet *);
@@ -566,7 +566,7 @@ bce_probe(device_t dev)
/* Print out the device identity. */
snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
- t->bce_name, (((pci_read_config(dev,
+ t->bce_name, (((pci_read_config(dev,
PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
(pci_read_config(dev, PCIR_REVID, 4) & 0xf));
@@ -593,57 +593,60 @@ bce_probe(device_t dev)
static void
bce_print_adapter_info(struct bce_softc *sc)
{
- int i = 0;
+ int i = 0;
DBENTER(BCE_VERBOSE_LOAD);
- BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
- printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
- ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
-
- /* Bus info. */
- if (sc->bce_flags & BCE_PCIE_FLAG) {
- printf("Bus (PCIe x%d, ", sc->link_width);
- switch (sc->link_speed) {
- case 1: printf("2.5Gbps); "); break;
- case 2: printf("5Gbps); "); break;
- default: printf("Unknown link speed); ");
+ if (bootverbose) {
+ BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
+ printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
+ 12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
+
+
+ /* Bus info. */
+ if (sc->bce_flags & BCE_PCIE_FLAG) {
+ printf("Bus (PCIe x%d, ", sc->link_width);
+ switch (sc->link_speed) {
+ case 1: printf("2.5Gbps); "); break;
+ case 2: printf("5Gbps); "); break;
+ default: printf("Unknown link speed); ");
+ }
+ } else {
+ printf("Bus (PCI%s, %s, %dMHz); ",
+ ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
+ ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
+ "32-bit" : "64-bit"), sc->bus_speed_mhz);
}
- } else {
- printf("Bus (PCI%s, %s, %dMHz); ",
- ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
- ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
- "32-bit" : "64-bit"), sc->bus_speed_mhz);
- }
- /* Firmware version and device features. */
- printf("B/C (%s); Flags (", sc->bce_bc_ver);
+ /* Firmware version and device features. */
+ printf("B/C (%s); Flags (", sc->bce_bc_ver);
-#ifdef BCE_JUMBO_HDRSPLIT
- printf("SPLT");
- i++;
-#endif
+ #ifdef BCE_JUMBO_HDRSPLIT
+ printf("SPLT");
+ i++;
+ #endif
- if (sc->bce_flags & BCE_USING_MSI_FLAG) {
- if (i > 0) printf("|");
- printf("MSI"); i++;
- }
+ if (sc->bce_flags & BCE_USING_MSI_FLAG) {
+ if (i > 0) printf("|");
+ printf("MSI"); i++;
+ }
- if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
- if (i > 0) printf("|");
- printf("MSI-X"); i++;
- }
+ if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
+ if (i > 0) printf("|");
+ printf("MSI-X"); i++;
+ }
- if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
- if (i > 0) printf("|");
- printf("2.5G"); i++;
- }
+ if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
+ if (i > 0) printf("|");
+ printf("2.5G"); i++;
+ }
- if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
- if (i > 0) printf("|");
- printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
- } else {
- printf(")\n");
+ if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
+ if (i > 0) printf("|");
+ printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
+ } else {
+ printf(")\n");
+ }
}
DBEXIT(BCE_VERBOSE_LOAD);
@@ -785,13 +788,13 @@ bce_attach(device_t dev)
(bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
sc->bce_msi_count = 1;
if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
- BCE_PRINTF("%s(%d): MSI allocation failed! error = %d\n",
- __FILE__, __LINE__, error);
+ BCE_PRINTF("%s(%d): MSI allocation failed! "
+ "error = %d\n", __FILE__, __LINE__, error);
sc->bce_msi_count = 0;
pci_release_msi(dev);
} else {
- DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI interrupt.\n",
- __FUNCTION__);
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
+ "interrupt.\n", __FUNCTION__);
sc->bce_flags |= BCE_USING_MSI_FLAG;
if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
@@ -848,10 +851,11 @@ bce_attach(device_t dev)
case BCE_CHIP_ID_5709_B0:
case BCE_CHIP_ID_5709_B1:
case BCE_CHIP_ID_5709_B2:
- BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n",
- __FILE__, __LINE__,
- (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
- (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
+ BCE_PRINTF("%s(%d): Unsupported controller "
+ "revision (%c%d)!\n", __FILE__, __LINE__,
+ (((pci_read_config(dev, PCIR_REVID, 4) &
+ 0xf0) >> 4) + 'A'), (pci_read_config(dev,
+ PCIR_REVID, 4) & 0xf));
rc = ENODEV;
goto bce_attach_fail;
}
@@ -1072,19 +1076,19 @@ bce_attach(device_t dev)
ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
BCE_PRINTF("%s(%d): Interface allocation failed!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
rc = ENXIO;
goto bce_attach_fail;
}
/* Initialize the ifnet interface. */
- ifp->if_softc = sc;
+ ifp->if_softc = sc;
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
- ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
- ifp->if_ioctl = bce_ioctl;
- ifp->if_start = bce_start;
- ifp->if_init = bce_init;
- ifp->if_mtu = ETHERMTU;
+ ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+ ifp->if_ioctl = bce_ioctl;
+ ifp->if_start = bce_start;
+ ifp->if_init = bce_init;
+ ifp->if_mtu = ETHERMTU;
if (bce_tso_enable) {
ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
@@ -1095,7 +1099,7 @@ bce_attach(device_t dev)
ifp->if_capabilities = BCE_IF_CAPABILITIES;
}
- ifp->if_capenable = ifp->if_capabilities;
+ ifp->if_capenable = ifp->if_capabilities;
/*
* Assume standard mbuf sizes for buffer allocation.
@@ -1105,16 +1109,17 @@ bce_attach(device_t dev)
#ifdef BCE_JUMBO_HDRSPLIT
sc->rx_bd_mbuf_alloc_size = MHLEN;
/* Make sure offset is 16 byte aligned for hardware. */
- sc->rx_bd_mbuf_align_pad = roundup2((MSIZE - MHLEN), 16) -
- (MSIZE - MHLEN);
- sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
- sc->rx_bd_mbuf_align_pad;
+ sc->rx_bd_mbuf_align_pad =
+ roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
+ sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
+ sc->rx_bd_mbuf_align_pad;
sc->pg_bd_mbuf_alloc_size = MCLBYTES;
#else
sc->rx_bd_mbuf_alloc_size = MCLBYTES;
- sc->rx_bd_mbuf_align_pad = roundup2(MCLBYTES, 16) - MCLBYTES;
- sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
- sc->rx_bd_mbuf_align_pad;
+ sc->rx_bd_mbuf_align_pad =
+ roundup2(MCLBYTES, 16) - MCLBYTES;
+ sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
+ sc->rx_bd_mbuf_align_pad;
#endif
ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD;
@@ -1126,14 +1131,14 @@ bce_attach(device_t dev)
else
ifp->if_baudrate = IF_Mbps(1000);
- /* Handle any special PHY initialization for SerDes PHYs. */
- bce_init_media(sc);
+ /* Handle any special PHY initialization for SerDes PHYs. */
+ bce_init_media(sc);
/* MII child bus by probing the PHY. */
if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd,
bce_ifmedia_sts)) {
BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
rc = ENXIO;
goto bce_attach_fail;
}
@@ -1155,7 +1160,7 @@ bce_attach(device_t dev)
if (rc) {
BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
bce_detach(dev);
goto bce_attach_exit;
}
@@ -1396,6 +1401,9 @@ bce_reg_wr_ind(struct bce_softc *sc, u32
static void
bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
{
+ DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X to "
+ "0x%08X\n", __FUNCTION__, val, offset);
+
bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
}
@@ -1411,7 +1419,12 @@ bce_shmem_wr(struct bce_softc *sc, u32 o
static u32
bce_shmem_rd(struct bce_softc *sc, u32 offset)
{
- return (bce_reg_rd_ind(sc, sc->bce_shmem_base + offset));
+ u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
+
+ DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
+ "0x%08X\n", __FUNCTION__, val, offset);
+
+ return val;
}
@@ -1430,9 +1443,9 @@ bce_ctx_rd(struct bce_softc *sc, u32 cid
{
u32 idx, offset, retry_cnt = 5, val;
- DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
- BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
- __FUNCTION__, cid_addr));
+ DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
+ cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
+ "address: 0x%08X.\n", __FUNCTION__, cid_addr));
offset = ctx_offset + cid_addr;
@@ -1450,8 +1463,8 @@ bce_ctx_rd(struct bce_softc *sc, u32 cid
if (val & BCE_CTX_CTX_CTRL_READ_REQ)
BCE_PRINTF("%s(%d); Unable to read CTX memory: "
- "cid_addr = 0x%08X, offset = 0x%08X!\n",
- __FILE__, __LINE__, cid_addr, ctx_offset);
+ "cid_addr = 0x%08X, offset = 0x%08X!\n",
+ __FILE__, __LINE__, cid_addr, ctx_offset);
val = REG_RD(sc, BCE_CTX_CTX_DATA);
} else {
@@ -1487,7 +1500,7 @@ bce_ctx_wr(struct bce_softc *sc, u32 cid
DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
- __FUNCTION__, cid_addr));
+ __FUNCTION__, cid_addr));
if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
@@ -1504,8 +1517,8 @@ bce_ctx_wr(struct bce_softc *sc, u32 cid
if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
BCE_PRINTF("%s(%d); Unable to write CTX memory: "
- "cid_addr = 0x%08X, offset = 0x%08X!\n",
- __FILE__, __LINE__, cid_addr, ctx_offset);
+ "cid_addr = 0x%08X, offset = 0x%08X!\n",
+ __FILE__, __LINE__, cid_addr, ctx_offset);
} else {
REG_WR(sc, BCE_CTX_DATA_ADR, offset);
@@ -1706,54 +1719,73 @@ bce_miibus_statchg(device_t dev)
val = REG_RD(sc, BCE_EMAC_MODE);
val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
- BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
- BCE_EMAC_MODE_25G);
+ BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
+ BCE_EMAC_MODE_25G);
- /* Set MII or GMII interface based on the speed negotiated by the PHY. */
+ /* Set MII or GMII interface based on the PHY speed. */
switch (IFM_SUBTYPE(mii->mii_media_active)) {
case IFM_10_T:
if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
- DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n");
+ DBPRINT(sc, BCE_INFO_PHY,
+ "Enabling 10Mb interface.\n");
val |= BCE_EMAC_MODE_PORT_MII_10;
break;
}
/* fall-through */
case IFM_100_TX:
- DBPRINT(sc, BCE_INFO, "Enabling MII interface.\n");
+ DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
val |= BCE_EMAC_MODE_PORT_MII;
break;
case IFM_2500_SX:
- DBPRINT(sc, BCE_INFO, "Enabling 2.5G MAC mode.\n");
+ DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
val |= BCE_EMAC_MODE_25G;
/* fall-through */
case IFM_1000_T:
case IFM_1000_SX:
- DBPRINT(sc, BCE_INFO, "Enabling GMII interface.\n");
+ DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
val |= BCE_EMAC_MODE_PORT_GMII;
break;
default:
- DBPRINT(sc, BCE_INFO, "Unknown speed, enabling default GMII "
- "interface.\n");
+ DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
+ "default GMII interface.\n");
val |= BCE_EMAC_MODE_PORT_GMII;
}
- /* Set half or full duplex based on the duplicity negotiated by the PHY. */
+ /* Set half or full duplex based on PHY settings. */
if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
- DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
+ DBPRINT(sc, BCE_INFO_PHY,
+ "Setting Half-Duplex interface.\n");
val |= BCE_EMAC_MODE_HALF_DUPLEX;
} else
- DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
+ DBPRINT(sc, BCE_INFO_PHY,
+ "Setting Full-Duplex interface.\n");
REG_WR(sc, BCE_EMAC_MODE, val);
-#if 0
- /* ToDo: Enable flow control support in brgphy and bge. */
/* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */
- if (mii->mii_media_active & IFM_FLAG0)
+ if (mii->mii_media_active & IFM_FLAG0) {
+ DBPRINT(sc, BCE_INFO_PHY,
+ "%s(): Enabling RX flow control.\n", __FUNCTION__);
BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
- if (mii->mii_media_active & IFM_FLAG1)
- BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
-#endif
+ } else {
+ DBPRINT(sc, BCE_INFO_PHY,
+ "%s(): Disabling RX flow control.\n", __FUNCTION__);
+ BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
+ }
+
+ if (mii->mii_media_active & IFM_FLAG1) {
+ DBPRINT(sc, BCE_INFO_PHY,
+ "%s(): Enabling TX flow control.\n", __FUNCTION__);
+ BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
+ sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
+ } else {
+ DBPRINT(sc, BCE_INFO_PHY,
+ "%s(): Disabling TX flow control.\n", __FUNCTION__);
+ BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
+ sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
+ }
+
+ /* ToDo: Update watermarks in bce_init_rx_context(). */
DBEXIT(BCE_VERBOSE_PHY);
}
@@ -1926,8 +1958,8 @@ bce_enable_nvram_access(struct bce_softc
val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
/* Enable both bits, even on read. */
- REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
- val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
+ REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
+ BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
DBEXIT(BCE_VERBOSE_NVRAM);
}
@@ -1951,9 +1983,8 @@ bce_disable_nvram_access(struct bce_soft
val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
/* Disable both bits, even after read. */
- REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
- val & ~(BCE_NVM_ACCESS_ENABLE_EN |
- BCE_NVM_ACCESS_ENABLE_WR_EN));
+ REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
+ ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
DBEXIT(BCE_VERBOSE_NVRAM);
}
@@ -1983,7 +2014,7 @@ bce_nvram_erase_page(struct bce_softc *s
/* Build an erase command. */
cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
- BCE_NVM_COMMAND_DOIT;
+ BCE_NVM_COMMAND_DOIT;
/*
* Clear the DONE bit separately, set the NVRAM adress to erase,
@@ -2026,8 +2057,8 @@ bce_nvram_erase_page_exit:
/* 0 on success and the 32 bit value read, positive value on failure. */
/****************************************************************************/
static int
-bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val,
- u32 cmd_flags)
+bce_nvram_read_dword(struct bce_softc *sc,
+ u32 offset, u8 *ret_val, u32 cmd_flags)
{
u32 cmd;
int i, rc = 0;
@@ -2040,8 +2071,8 @@ bce_nvram_read_dword(struct bce_softc *s
/* Calculate the offset for buffered flash if translation is used. */
if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
offset = ((offset / sc->bce_flash_info->page_size) <<
- sc->bce_flash_info->page_bits) +
- (offset % sc->bce_flash_info->page_size);
+ sc->bce_flash_info->page_bits) +
+ (offset % sc->bce_flash_info->page_size);
}
/*
@@ -2070,8 +2101,8 @@ bce_nvram_read_dword(struct bce_softc *s
/* Check for errors. */
if (i >= NVRAM_TIMEOUT_COUNT) {
- BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n",
- __FILE__, __LINE__, offset);
+ BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
+ "offset 0x%08X!\n", __FILE__, __LINE__, offset);
rc = EBUSY;
}
@@ -2106,8 +2137,8 @@ bce_nvram_write_dword(struct bce_softc *
/* Calculate the offset for buffered flash if translation is used. */
if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
offset = ((offset / sc->bce_flash_info->page_size) <<
- sc->bce_flash_info->page_bits) +
- (offset % sc->bce_flash_info->page_size);
+ sc->bce_flash_info->page_bits) +
+ (offset % sc->bce_flash_info->page_size);
}
/*
@@ -2129,8 +2160,8 @@ bce_nvram_write_dword(struct bce_softc *
break;
}
if (j >= NVRAM_TIMEOUT_COUNT) {
- BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n",
- __FILE__, __LINE__, offset);
+ BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
+ "offset 0x%08X\n", __FILE__, __LINE__, offset);
rc = EBUSY;
}
@@ -2232,7 +2263,7 @@ bce_init_nvram(struct bce_softc *sc)
if (j == entry_count) {
sc->bce_flash_info = NULL;
BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
rc = ENODEV;
}
@@ -2246,8 +2277,8 @@ bce_init_nvram_get_flash_size:
sc->bce_flash_size = sc->bce_flash_info->total_size;
DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
- __FUNCTION__, sc->bce_flash_info->name,
- sc->bce_flash_info->total_size);
+ __FUNCTION__, sc->bce_flash_info->name,
+ sc->bce_flash_info->total_size);
DBEXIT(BCE_VERBOSE_NVRAM);
return rc;
@@ -2604,7 +2635,8 @@ bce_nvram_test(struct bce_softc *sc)
* the magic value at offset 0.
*/
if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
- BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", __FILE__, __LINE__);
+ BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
+ __FILE__, __LINE__);
goto bce_nvram_test_exit;
}
@@ -2615,9 +2647,9 @@ bce_nvram_test(struct bce_softc *sc)
magic = bce_be32toh(buf[0]);
if (magic != BCE_NVRAM_MAGIC) {
rc = ENODEV;
- BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, "
- "Found: 0x%08X\n",
- __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
+ BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
+ "Expected: 0x%08X, Found: 0x%08X\n",
+ __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
goto bce_nvram_test_exit;
}
@@ -2626,26 +2658,27 @@ bce_nvram_test(struct bce_softc *sc)
* configuration data.
*/
if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
- BCE_PRINTF("%s(%d): Unable to read Manufacturing Information from "
- "NVRAM!\n", __FILE__, __LINE__);
+ BCE_PRINTF("%s(%d): Unable to read manufacturing "
+ "Information from NVRAM!\n", __FILE__, __LINE__);
goto bce_nvram_test_exit;
}
csum = ether_crc32_le(data, 0x100);
if (csum != BCE_CRC32_RESIDUAL) {
rc = ENODEV;
- BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! "
- "Expected: 0x%08X, Found: 0x%08X\n",
- __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
+ BCE_PRINTF("%s(%d): Invalid manufacturing information "
+ "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
+ __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
goto bce_nvram_test_exit;
}
csum = ether_crc32_le(data + 0x100, 0x100);
if (csum != BCE_CRC32_RESIDUAL) {
rc = ENODEV;
- BCE_PRINTF("%s(%d): Invalid Feature Configuration Information "
- "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
- __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
+ BCE_PRINTF("%s(%d): Invalid feature configuration "
+ "information NVRAM CRC! Expected: 0x%08X, "
+ "Found: 08%08X\n", __FILE__, __LINE__,
+ BCE_CRC32_RESIDUAL, csum);
}
bce_nvram_test_exit:
@@ -2666,7 +2699,7 @@ bce_get_media(struct bce_softc *sc)
{
u32 val;
- DBENTER(BCE_VERBOSE);
+ DBENTER(BCE_VERBOSE_PHY);
/* Assume PHY address for copper controllers. */
sc->bce_phy_addr = 1;
@@ -2692,10 +2725,10 @@ bce_get_media(struct bce_softc *sc)
}
if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
- strap = (val &
+ strap = (val &
BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
else
- strap = (val &
+ strap = (val &
BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
if (pci_get_function(sc->bce_dev) == 0) {
@@ -2744,7 +2777,7 @@ bce_get_media(struct bce_softc *sc)
val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
- sc->bce_phy_flags |=
+ sc->bce_phy_flags |=
BCE_PHY_2_5G_CAPABLE_FLAG;
DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
"capable adapter\n");
@@ -2758,7 +2791,7 @@ bce_get_media_exit:
DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
"Using PHY address %d.\n", sc->bce_phy_addr);
- DBEXIT(BCE_VERBOSE);
+ DBEXIT(BCE_VERBOSE_PHY);
}
@@ -3056,7 +3089,9 @@ bce_dma_map_addr(void *arg, bus_dma_segm
/* Simulate a mapping failure. */
DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
- error = ENOMEM);
+ error = ENOMEM);
+
+ /* ToDo: How to increment debug sim_count variable here? */
/* Check for an error and signal the caller that an error occurred. */
if (error) {
@@ -3154,7 +3189,7 @@ bce_dma_alloc(device_t dev)
goto bce_dma_alloc_exit;
}
- DBPRINT(sc, BCE_INFO, "%s(): status_block_paddr = 0x%jX\n",
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
__FUNCTION__, (uintmax_t) sc->status_block_paddr);
/*
@@ -3193,7 +3228,7 @@ bce_dma_alloc(device_t dev)
goto bce_dma_alloc_exit;
}
- DBPRINT(sc, BCE_INFO, "%s(): stats_block_paddr = 0x%jX\n",
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
__FUNCTION__, (uintmax_t) sc->stats_block_paddr);
/* BCM5709 uses host memory as cache for context memory. */
@@ -3217,8 +3252,8 @@ bce_dma_alloc(device_t dev)
BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
0, NULL, NULL, &sc->ctx_tag)) {
- BCE_PRINTF("%s(%d): Could not allocate CTX DMA tag!\n",
- __FILE__, __LINE__);
+ BCE_PRINTF("%s(%d): Could not allocate CTX "
+ "DMA tag!\n", __FILE__, __LINE__);
rc = ENOMEM;
goto bce_dma_alloc_exit;
}
@@ -3248,8 +3283,9 @@ bce_dma_alloc(device_t dev)
goto bce_dma_alloc_exit;
}
- DBPRINT(sc, BCE_INFO, "%s(): ctx_paddr[%d] = 0x%jX\n",
- __FUNCTION__, i, (uintmax_t) sc->ctx_paddr[i]);
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
+ "= 0x%jX\n", __FUNCTION__, i,
+ (uintmax_t) sc->ctx_paddr[i]);
}
}
@@ -3262,15 +3298,15 @@ bce_dma_alloc(device_t dev)
sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
NULL, NULL, &sc->tx_bd_chain_tag)) {
- BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain "
- "DMA tag!\n", __FILE__, __LINE__);
+ BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
+ "chain DMA tag!\n", __FILE__, __LINE__);
rc = ENOMEM;
goto bce_dma_alloc_exit;
}
for (i = 0; i < TX_PAGES; i++) {
- if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
+ if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
(void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT,
&sc->tx_bd_chain_map[i])) {
BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
@@ -3291,8 +3327,9 @@ bce_dma_alloc(device_t dev)
goto bce_dma_alloc_exit;
}
- DBPRINT(sc, BCE_INFO, "%s(): tx_bd_chain_paddr[%d] = 0x%jX\n",
- __FUNCTION__, i, (uintmax_t) sc->tx_bd_chain_paddr[i]);
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
+ "0x%jX\n", __FUNCTION__, i,
+ (uintmax_t) sc->tx_bd_chain_paddr[i]);
}
/* Check the required size before mapping to conserve resources. */
@@ -3368,8 +3405,9 @@ bce_dma_alloc(device_t dev)
goto bce_dma_alloc_exit;
}
- DBPRINT(sc, BCE_INFO, "%s(): rx_bd_chain_paddr[%d] = 0x%jX\n",
- __FUNCTION__, i, (uintmax_t) sc->rx_bd_chain_paddr[i]);
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
+ "0x%jX\n", __FUNCTION__, i,
+ (uintmax_t) sc->rx_bd_chain_paddr[i]);
}
/*
@@ -3383,9 +3421,10 @@ bce_dma_alloc(device_t dev)
#endif
max_segments = 1;
- DBPRINT(sc, BCE_INFO, "%s(): Creating rx_mbuf_tag (max size = 0x%jX "
- "max segments = %d, max segment size = 0x%jX)\n", __FUNCTION__,
- (uintmax_t) max_size, max_segments, (uintmax_t) max_seg_size);
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
+ "(max size = 0x%jX max segments = %d, max segment "
+ "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
+ max_segments, (uintmax_t) max_seg_size);
if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
@@ -3429,7 +3468,7 @@ bce_dma_alloc(device_t dev)
(void **)&sc->pg_bd_chain[i], BUS_DMA_NOWAIT,
&sc->pg_bd_chain_map[i])) {
BCE_PRINTF("%s(%d): Could not allocate page "
- "descriptor chain DMA memory!\n",
+ "descriptor chain DMA memory!\n",
__FILE__, __LINE__);
rc = ENOMEM;
goto bce_dma_alloc_exit;
@@ -3437,7 +3476,7 @@ bce_dma_alloc(device_t dev)
bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
- error = bus_dmamap_load(sc->pg_bd_chain_tag,
+ error = bus_dmamap_load(sc->pg_bd_chain_tag,
sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
&sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
@@ -3449,8 +3488,9 @@ bce_dma_alloc(device_t dev)
goto bce_dma_alloc_exit;
}
- DBPRINT(sc, BCE_INFO, "%s(): pg_bd_chain_paddr[%d] = 0x%jX\n",
- __FUNCTION__, i, (uintmax_t) sc->pg_bd_chain_paddr[i]);
+ DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
+ "0x%jX\n", __FUNCTION__, i,
+ (uintmax_t) sc->pg_bd_chain_paddr[i]);
}
/*
@@ -3524,7 +3564,7 @@ bce_release_resources(struct bce_softc *
if (sc->bce_res_mem != NULL) {
DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
- bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
+ bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
sc->bce_res_mem);
}
@@ -3582,7 +3622,7 @@ bce_fw_sync(struct bce_softc *sc, u32 ms
DELAY(1000);
}
- /* If we've timed out, tell the bootcode that we've stopped waiting. */
+ /* If we've timed out, tell bootcode that we've stopped waiting. */
if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
@@ -4319,22 +4359,22 @@ bce_init_cpus(struct bce_softc *sc)
(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
- bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
- sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
- bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
- sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
+ bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
+ sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
+ bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
+ sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
} else {
- bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
- sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
- bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
- sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
+ bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
+ sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
+ bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
+ sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
}
} else {
- bce_load_rv2p_fw(sc, bce_rv2p_proc1,
- sizeof(bce_rv2p_proc1), RV2P_PROC1);
+ bce_load_rv2p_fw(sc, bce_rv2p_proc1,
+ sizeof(bce_rv2p_proc1), RV2P_PROC1);
bce_load_rv2p_fw(sc, bce_rv2p_proc2,
- sizeof(bce_rv2p_proc2), RV2P_PROC2);
+ sizeof(bce_rv2p_proc2), RV2P_PROC2);
}
bce_init_rxp_cpu(sc);
@@ -4373,7 +4413,7 @@ bce_init_ctx(struct bce_softc *sc)
* in host memory so prepare the host memory
* for access.
*/
- val = BCE_CTX_COMMAND_ENABLED |
+ val = BCE_CTX_COMMAND_ENABLED |
BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
val |= (BCM_PAGE_BITS - 8) << 16;
REG_WR(sc, BCE_CTX_COMMAND, val);
@@ -4406,7 +4446,7 @@ bce_init_ctx(struct bce_softc *sc)
/* Verify the context memory write was successful. */
for (j = 0; j < retry_cnt; j++) {
val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
- if ((val &
+ if ((val &
BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
break;
DELAY(5);
@@ -4461,6 +4501,7 @@ bce_get_mac_addr(struct bce_softc *sc)
u32 mac_lo = 0, mac_hi = 0;
DBENTER(BCE_VERBOSE_RESET);
+
/*
* The NetXtreme II bootcode populates various NIC
* power-on and runtime configuration items in a
@@ -4475,7 +4516,7 @@ bce_get_mac_addr(struct bce_softc *sc)
if ((mac_lo == 0) && (mac_hi == 0)) {
BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
} else {
sc->eaddr[0] = (u_char)(mac_hi >> 8);
sc->eaddr[1] = (u_char)(mac_hi >> 0);
@@ -4485,7 +4526,8 @@ bce_get_mac_addr(struct bce_softc *sc)
sc->eaddr[5] = (u_char)(mac_lo >> 0);
}
- DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
+ DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
+ "address = %6D\n", sc->eaddr, ":");
DBEXIT(BCE_VERBOSE_RESET);
}
@@ -4505,14 +4547,15 @@ bce_set_mac_addr(struct bce_softc *sc)
/* ToDo: Add support for setting multiple MAC addresses. */
DBENTER(BCE_VERBOSE_RESET);
- DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":");
+ DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
+ "%6D\n", sc->eaddr, ":");
val = (mac_addr[0] << 8) | mac_addr[1];
REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
- (mac_addr[4] << 8) | mac_addr[5];
+ (mac_addr[4] << 8) | mac_addr[5];
REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
@@ -4598,20 +4641,20 @@ bce_reset(struct bce_softc *sc, u32 rese
DBENTER(BCE_VERBOSE_RESET);
DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
- __FUNCTION__, reset_code);
+ __FUNCTION__, reset_code);
/* Wait for pending PCI transactions to complete. */
REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
- BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
- BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
- BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
- BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
+ BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
+ BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
+ BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
+ BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
DELAY(5);
/* Disable DMA */
if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
- (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
+ (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
@@ -4634,26 +4677,26 @@ bce_reset(struct bce_softc *sc, u32 rese
/* Chip reset. */
if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
- (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
+ (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
REG_RD(sc, BCE_MISC_COMMAND);
DELAY(5);
val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
- BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
+ BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
} else {
val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
- BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
- BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
+ BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+ BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
/* Allow up to 30us for reset to complete. */
for (i = 0; i < 10; i++) {
val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
- BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
+ BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
break;
}
DELAY(10);
@@ -4661,9 +4704,9 @@ bce_reset(struct bce_softc *sc, u32 rese
/* Check that reset completed successfully. */
if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
- BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
+ BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
BCE_PRINTF("%s(%d): Reset failed!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
rc = EBUSY;
goto bce_reset_exit;
}
@@ -4673,7 +4716,7 @@ bce_reset(struct bce_softc *sc, u32 rese
val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
if (val != 0x01020304) {
BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
- __FILE__, __LINE__);
+ __FILE__, __LINE__);
rc = ENODEV;
goto bce_reset_exit;
}
@@ -4685,8 +4728,8 @@ bce_reset(struct bce_softc *sc, u32 rese
/* Wait for the firmware to finish its initialization. */
rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
if (rc)
- BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n",
- __FILE__, __LINE__);
+ BCE_PRINTF("%s(%d): Firmware did not complete "
+ "initialization!\n", __FILE__, __LINE__);
bce_reset_exit:
DBEXIT(BCE_VERBOSE_RESET);
@@ -4709,13 +4752,13 @@ bce_chipinit(struct bce_softc *sc)
* channels and PCI clock compensation delay.
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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