svn commit: r194420 - in stable/7/sys: . contrib/pf dev/msk

[Pyun YongHyeon]

Author: yongari
Date: Thu Jun 18 05:20:02 2009
New Revision: 194420
URL: http://svn.freebsd.org/changeset/base/194420

Log:
  MFC r192734:
    Add preliminary Yukon FE+ support and register definitions.
    Yukon FE+ is fast ethernet controller and uses new descriptor
    format. Since I don't have this controller, the support code was
    written from guess and various feedback from enthusiastic users.
    Thanks to all users who patiently tested my initial patches.
    Special thanks to Tanguy Bouzeloc who fixed critical bug of initial
    patch.
  
    Tested by:	bz, Tanguy Bouzeloc ( the.zauron <> gmail dot com )
  		Bruce Cran ( bruce <> cran dot org dot uk )
  		Michael Reifenberger ( mike <> reifenberger dot com )
  		Stephen Montgomery-Smith ( stephen <> missouri dot edu )

Modified:
  stable/7/sys/   (props changed)
  stable/7/sys/contrib/pf/   (props changed)
  stable/7/sys/dev/msk/if_msk.c
  stable/7/sys/dev/msk/if_mskreg.h

Modified: stable/7/sys/dev/msk/if_msk.c
==============================================================================
--- stable/7/sys/dev/msk/if_msk.c	Thu Jun 18 05:16:19 2009	(r194419)
+++ stable/7/sys/dev/msk/if_msk.c	Thu Jun 18 05:20:02 2009	(r194420)
@@ -220,7 +220,8 @@ static const char *model_name[] = {
         "Yukon EC Ultra",
         "Yukon Unknown",
         "Yukon EC",
-        "Yukon FE"
+        "Yukon FE",
+        "Yukon FE+"
 };
 
 static int mskc_probe(device_t);
@@ -1116,6 +1117,7 @@ msk_phy_power(struct msk_softc *sc, int 
 			}
 			break;
 		case CHIP_ID_YUKON_EC_U:
+		case CHIP_ID_YUKON_FE_P:
 			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 
 			/* Enable all clocks. */
@@ -1579,7 +1581,7 @@ mskc_attach(device_t dev)
 	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
 	/* Bail out if chip is not recognized. */
 	if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
-	    sc->msk_hw_id > CHIP_ID_YUKON_FE) {
+	    sc->msk_hw_id > CHIP_ID_YUKON_FE_P) {
 		device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
 		    sc->msk_hw_id, sc->msk_hw_rev);
 		mtx_destroy(&sc->msk_mtx);
@@ -1641,6 +1643,10 @@ mskc_attach(device_t dev)
 		sc->msk_clock = 100;	/* 100 Mhz */
 		sc->msk_pflags |= MSK_FLAG_FASTETHER;
 		break;
+	case CHIP_ID_YUKON_FE_P:
+		sc->msk_clock = 50;	/* 50 Mhz */
+		sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2;
+		break;
 	case CHIP_ID_YUKON_XL:
 		sc->msk_clock = 156;	/* 156 Mhz */
 		sc->msk_pflags |= MSK_FLAG_JUMBO;
@@ -3512,6 +3518,7 @@ msk_init_locked(struct msk_if_softc *sc_
 	struct mii_data	 *mii;
 	uint16_t eaddr[ETHER_ADDR_LEN / 2];
 	uint16_t gmac;
+	uint32_t reg;
 	int error, i;
 
 	MSK_IF_LOCK_ASSERT(sc_if);
@@ -3590,8 +3597,10 @@ msk_init_locked(struct msk_if_softc *sc_
 	/* Configure Rx MAC FIFO. */
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
-	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
-	    GMF_OPER_ON | GMF_RX_F_FL_ON);
+	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
+	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P)
+		reg |= GMF_RX_OVER_ON;
+	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
 
 	/* Set receive filter. */
 	msk_rxfilter(sc_if);

Modified: stable/7/sys/dev/msk/if_mskreg.h
==============================================================================
--- stable/7/sys/dev/msk/if_mskreg.h	Thu Jun 18 05:16:19 2009	(r194419)
+++ stable/7/sys/dev/msk/if_mskreg.h	Thu Jun 18 05:20:02 2009	(r194420)
@@ -828,6 +828,7 @@
 #define CHIP_ID_YUKON_EC_U	0xb4 /* Chip ID for YUKON-2 EC Ultra */
 #define CHIP_ID_YUKON_EC	0xb6 /* Chip ID for YUKON-2 EC */
 #define CHIP_ID_YUKON_FE	0xb7 /* Chip ID for YUKON-2 FE */
+#define CHIP_ID_YUKON_FE_P	0xb8 /* Chip ID for YUKON-2 FE+ */
 
 #define	CHIP_REV_YU_XL_A0	0 /* Chip Rev. for Yukon-2 A0 */
 #define	CHIP_REV_YU_XL_A1	1 /* Chip Rev. for Yukon-2 A1 */
@@ -841,6 +842,8 @@
 #define	CHIP_REV_YU_EC_U_A0	1
 #define	CHIP_REV_YU_EC_U_A1	2
 
+#define	CHIP_REV_YU_FE_P_A0	0 /* Chip Rev. for Yukon-2 FE+ A0 */
+
 /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
 #define Y2_STATUS_LNK2_INAC	BIT_7	/* Status Link 2 inactiv (0 = activ) */
 #define Y2_CLK_GAT_LNK2_DIS	BIT_6	/* Disable clock gating Link 2 */
@@ -1855,6 +1858,10 @@
 #define RX_TRUNC_OFF		BIT_26	/* disable packet truncation */
 #define RX_VLAN_STRIP_ON	BIT_25	/* enable  VLAN stripping */
 #define RX_VLAN_STRIP_OFF	BIT_24	/* disable VLAN stripping */
+#define GMF_RX_OVER_ON		BIT_19	/* enable flushing on receive overrun */
+#define GMF_RX_OVER_OFF		BIT_18	/* disable flushing on receive overrun */
+#define GMF_ASF_RX_OVER_ON	BIT_17	/* enable flushing of ASF when overrun */
+#define GMF_ASF_RX_OVER_OFF	BIT_16	/* disable flushing of ASF when overrun */
 #define GMF_WP_TST_ON		BIT_14	/* Write Pointer Test On */
 #define GMF_WP_TST_OFF		BIT_13	/* Write Pointer Test Off */
 #define GMF_WP_STEP		BIT_12	/* Write Pointer Step/Increment */