svn commit: r194075 - in stable/7/sys: . amd64/amd64 amd64/include contrib/pf dev/ath/ath_hal i386/i386 i386/include

[Jung-uk Kim]

Author: jkim
Date: Fri Jun 12 20:41:44 2009
New Revision: 194075
URL: http://svn.freebsd.org/changeset/base/194075

Log:
  MFC:	r175904, r175905, r186009
  
  Sync amd64 and i386 CPUID feature flags with -CURRENT.
  
  - amd64 only:	DTES64, SSE4.1, SSE4.2, x2APIC, POPCNT
  - both:		ABM, SSE4A, MAS, OSVW, IBS, SSE5, SKINIT, WDT
  
  PR:		kern/135202

Modified:
  stable/7/sys/   (props changed)
  stable/7/sys/amd64/amd64/identcpu.c
  stable/7/sys/amd64/include/specialreg.h
  stable/7/sys/contrib/pf/   (props changed)
  stable/7/sys/dev/ath/ath_hal/   (props changed)
  stable/7/sys/i386/i386/identcpu.c
  stable/7/sys/i386/include/specialreg.h

Modified: stable/7/sys/amd64/amd64/identcpu.c
==============================================================================
--- stable/7/sys/amd64/amd64/identcpu.c	Fri Jun 12 20:29:55 2009	(r194074)
+++ stable/7/sys/amd64/amd64/identcpu.c	Fri Jun 12 20:41:44 2009	(r194075)
@@ -223,7 +223,7 @@ printcpuinfo(void)
 				"\020"
 				"\001SSE3"	/* SSE3 */
 				"\002<b1>"
-				"\003RSVD2"	/* "Reserved" bit 2 */
+				"\003DTES64"	/* 64-bit Debug Trace */
 				"\004MON"	/* MONITOR/MWAIT Instructions */
 				"\005DS_CPL"	/* CPL Qualified Debug Store */
 				"\006VMX"	/* Virtual Machine Extensions */
@@ -240,11 +240,11 @@ printcpuinfo(void)
 				"\021<b16>"
 				"\022<b17>"
 				"\023DCA"	/* Direct Cache Access */
-				"\024<b19>"
-				"\025<b20>"
-				"\026<b21>"
+				"\024SSE4.1"
+				"\025SSE4.2"
+				"\026x2APIC"	/* xAPIC Extensions */
 				"\027<b22>"
-				"\030<b23>"
+				"\030POPCNT"
 				"\031<b24>"
 				"\032<b25>"
 				"\033XSAVE"
@@ -311,15 +311,15 @@ printcpuinfo(void)
 				"\003SVM"	/* Secure Virtual Mode */
 				"\004ExtAPIC"	/* Extended APIC register */
 				"\005CR8"	/* CR8 in legacy mode */
-				"\006<b5>"
-				"\007<b6>"
-				"\010<b7>"
+				"\006ABM"	/* LZCNT instruction */
+				"\007SSE4A"	/* SSE4A */
+				"\010MAS"	/* Misaligned SSE mode */
 				"\011Prefetch"	/* 3DNow! Prefetch/PrefetchW */
-				"\012<b9>"
-				"\013<b10>"
-				"\014<b11>"
-				"\015<b12>"
-				"\016<b13>"
+				"\012OSVW"	/* OS visible workaround */
+				"\013IBS"	/* Instruction based sampling */
+				"\014SSE5"	/* SSE5 */
+				"\015SKINIT"	/* SKINIT/STGI */
+				"\016WDT"	/* Watchdog timer */
 				"\017<b14>"
 				"\020<b15>"
 				"\021<b16>"

Modified: stable/7/sys/amd64/include/specialreg.h
==============================================================================
--- stable/7/sys/amd64/include/specialreg.h	Fri Jun 12 20:29:55 2009	(r194074)
+++ stable/7/sys/amd64/include/specialreg.h	Fri Jun 12 20:41:44 2009	(r194075)
@@ -113,6 +113,7 @@
 #define	CPUID_PBE	0x80000000
 
 #define	CPUID2_SSE3	0x00000001
+#define	CPUID2_DTES64	0x00000004
 #define	CPUID2_MON	0x00000008
 #define	CPUID2_DS_CPL	0x00000010
 #define	CPUID2_VMX	0x00000020
@@ -125,6 +126,10 @@
 #define	CPUID2_XTPR	0x00004000
 #define	CPUID2_PDCM	0x00008000
 #define	CPUID2_DCA	0x00040000
+#define	CPUID2_SSE41	0x00080000
+#define	CPUID2_SSE42	0x00100000
+#define	CPUID2_X2APIC	0x00200000
+#define	CPUID2_POPCNT	0x00800000
 
 /*
  * Important bits in the AMD extended cpuid flags
@@ -145,7 +150,15 @@
 #define	AMDID2_SVM	0x00000004
 #define	AMDID2_EXT_APIC	0x00000008
 #define	AMDID2_CR8	0x00000010
+#define	AMDID2_ABM	0x00000020
+#define	AMDID2_SSE4A	0x00000040
+#define	AMDID2_MAS	0x00000080
 #define	AMDID2_PREFETCH	0x00000100
+#define	AMDID2_OSVW	0x00000200
+#define	AMDID2_IBS	0x00000400
+#define	AMDID2_SSE5	0x00000800
+#define	AMDID2_SKINIT	0x00001000
+#define	AMDID2_WDT	0x00002000
 
 /*
  * CPUID instruction 1 eax info

Modified: stable/7/sys/i386/i386/identcpu.c
==============================================================================
--- stable/7/sys/i386/i386/identcpu.c	Fri Jun 12 20:29:55 2009	(r194074)
+++ stable/7/sys/i386/i386/identcpu.c	Fri Jun 12 20:41:44 2009	(r194075)
@@ -808,15 +808,15 @@ printcpuinfo(void)
 				"\003SVM"	/* Secure Virtual Mode */
 				"\004ExtAPIC"	/* Extended APIC register */
 				"\005CR8"	/* CR8 in legacy mode */
-				"\006<b5>"
-				"\007<b6>"
-				"\010<b7>"
+				"\006ABM"	/* LZCNT instruction */
+				"\007SSE4A"	/* SSE4A */
+				"\010MAS"	/* Misaligned SSE mode */
 				"\011Prefetch"	/* 3DNow! Prefetch/PrefetchW */
-				"\012<b9>"
-				"\013<b10>"
-				"\014<b11>"
-				"\015<b12>"
-				"\016<b13>"
+				"\012OSVW"	/* OS visible workaround */
+				"\013IBS"	/* Instruction based sampling */
+				"\014SSE5"	/* SSE5 */
+				"\015SKINIT"	/* SKINIT/STGI */
+				"\016WDT"	/* Watchdog timer */
 				"\017<b14>"
 				"\020<b15>"
 				"\021<b16>"

Modified: stable/7/sys/i386/include/specialreg.h
==============================================================================
--- stable/7/sys/i386/include/specialreg.h	Fri Jun 12 20:29:55 2009	(r194074)
+++ stable/7/sys/i386/include/specialreg.h	Fri Jun 12 20:41:44 2009	(r194075)
@@ -147,7 +147,15 @@
 #define	AMDID2_SVM	0x00000004
 #define	AMDID2_EXT_APIC	0x00000008
 #define	AMDID2_CR8	0x00000010
+#define	AMDID2_ABM	0x00000020
+#define	AMDID2_SSE4A	0x00000040
+#define	AMDID2_MAS	0x00000080
 #define	AMDID2_PREFETCH	0x00000100
+#define	AMDID2_OSVW	0x00000200
+#define	AMDID2_IBS	0x00000400
+#define	AMDID2_SSE5	0x00000800
+#define	AMDID2_SKINIT	0x00001000
+#define	AMDID2_WDT	0x00002000
 
 /*
  * CPUID instruction 1 eax info