svn commit: r256443 - in stable/9: contrib/binutils/gas/config contrib/binutils/opcodes sys/amd64/amd64
Dimitry Andric
dim at FreeBSD.org
Mon Oct 14 15:06:49 UTC 2013
Author: dim
Date: Mon Oct 14 15:06:47 2013
New Revision: 256443
URL: http://svnweb.freebsd.org/changeset/base/256443
Log:
MFC r247012 (by jmg):
add support for AES and PCLMULQDQ instructions to binutils...
Thanks to Mike Belopuhov for the pointer to the OpenBSD patch, though
OpenBSD's gcc is very different that it only helped w/ where to modify,
not how... Thanks to jhb for some early reviews...
Reviewed by: imp, kib
MFC r247117 (by jmg):
reorder so all the flags are together and make the PCLMUL flag unique..
This fixes the problem on amd64 miscompiling mpboot.s causing boot
issues... We are still using gas for a few files in the kernel...
Submitted by: kib
MFC r255192 (by jhb):
Add support for the 'invpcid' instruction to binutils and DDB's
disassembler on amd64.
MFC r256112:
Add support for assembling and disassembling Intel Random Number
Generator extensions (e.g. the 'rdrand' mnemonic) to our copy of
binutils.
Obtained from: OpenBSD, via pfg
Modified:
stable/9/contrib/binutils/gas/config/tc-i386.c
stable/9/contrib/binutils/opcodes/i386-dis.c
stable/9/contrib/binutils/opcodes/i386-opc.h
stable/9/contrib/binutils/opcodes/i386-opc.tbl
stable/9/contrib/binutils/opcodes/i386-tbl.h
stable/9/sys/amd64/amd64/db_disasm.c
Directory Properties:
stable/9/contrib/binutils/ (props changed)
stable/9/sys/ (props changed)
Modified: stable/9/contrib/binutils/gas/config/tc-i386.c
==============================================================================
--- stable/9/contrib/binutils/gas/config/tc-i386.c Mon Oct 14 12:11:19 2013 (r256442)
+++ stable/9/contrib/binutils/gas/config/tc-i386.c Mon Oct 14 15:06:47 2013 (r256443)
@@ -3981,7 +3981,7 @@ output_insn (void)
SSE4 instructions have 3 bytes. We may use one more higher
byte to specify a prefix the instruction requires. Exclude
instructions which are in both SSE4 and ABM. */
- if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+ if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4 | CpuAES | CpuPCLMUL)) != 0
&& (i.tm.cpu_flags & CpuABM) == 0)
{
if (i.tm.base_opcode & 0xff000000)
@@ -3990,7 +3990,8 @@ output_insn (void)
goto check_prefix;
}
}
- else if (i.tm.base_opcode == 0x660f3880 || i.tm.base_opcode == 0x660f3881)
+ else if (i.tm.base_opcode == 0x660f3880 || i.tm.base_opcode == 0x660f3881
+ || i.tm.base_opcode == 0x660f3882)
{
/* invept and invvpid are 3 byte instructions with a
mandatory prefix. */
@@ -4033,14 +4034,15 @@ output_insn (void)
}
else
{
- if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
+ if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4 | CpuAES | CpuPCLMUL)) != 0
&& (i.tm.cpu_flags & CpuABM) == 0)
{
p = frag_more (3);
*p++ = (i.tm.base_opcode >> 16) & 0xff;
}
else if (i.tm.base_opcode == 0x660f3880 ||
- i.tm.base_opcode == 0x660f3881)
+ i.tm.base_opcode == 0x660f3881 ||
+ i.tm.base_opcode == 0x660f3882)
{
p = frag_more (3);
*p++ = (i.tm.base_opcode >> 16) & 0xff;
Modified: stable/9/contrib/binutils/opcodes/i386-dis.c
==============================================================================
--- stable/9/contrib/binutils/opcodes/i386-dis.c Mon Oct 14 12:11:19 2013 (r256442)
+++ stable/9/contrib/binutils/opcodes/i386-dis.c Mon Oct 14 15:06:47 2013 (r256443)
@@ -543,6 +543,14 @@ fetch_data (struct disassemble_info *inf
#define PREGRP97 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 97 } }
#define PREGRP98 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 98 } }
#define PREGRP99 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 99 } }
+#define PREGRP100 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 100 } }
+#define PREGRP101 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 101 } }
+#define PREGRP102 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 102 } }
+#define PREGRP103 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 103 } }
+#define PREGRP104 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 104 } }
+#define PREGRP105 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 105 } }
+#define PREGRP106 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 106 } }
+#define PREGRP107 NULL, { { NULL, USE_PREFIX_USER_TABLE }, { NULL, 107 } }
#define X86_64_0 NULL, { { NULL, X86_64_SPECIAL }, { NULL, 0 } }
@@ -1319,7 +1327,7 @@ static const unsigned char threebyte_0x3
/* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
/* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
/* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
+ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1, /* df */
/* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
/* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
/* ------------------------------- */
@@ -1382,7 +1390,7 @@ static const unsigned char threebyte_0x3
/* 10 */ 0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
/* 20 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 2f */
/* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */
- /* 40 */ 1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
+ /* 40 */ 1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
/* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 5f */
/* 60 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0, /* 6f */
/* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 7f */
@@ -1391,7 +1399,7 @@ static const unsigned char threebyte_0x3
/* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
/* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
/* c0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */
- /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* df */
+ /* d0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1, /* df */
/* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ef */
/* f0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* ff */
/* ------------------------------- */
@@ -2605,6 +2613,70 @@ static const struct dis386 prefix_user_t
{ "invvpid",{ Gm, Mo } },
{ "(bad)", { XX } },
},
+
+ /* PREGRP100 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "aesimc", { XM, EXx } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP101 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "aesenc",{ XM, EXx } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP102 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "aesenclast", { XM, EXx } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP103 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "aesdec", { XM, EXx } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP104 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "aesdeclast", { XM, EXx } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP105 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "aeskeygenassist", { XM, EXx, Ib } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP106 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "pclmulqdq", { XM, EXx, Ib } },
+ { "(bad)", { XX } },
+ },
+
+ /* PREGRP107 */
+ {
+ { "(bad)", { XX } },
+ { "(bad)", { XX } },
+ { "invpcid",{ Gm, Mo } },
+ { "(bad)", { XX } },
+ },
};
static const struct dis386 x86_64_table[][2] = {
@@ -2776,7 +2848,7 @@ static const struct dis386 three_byte_ta
/* 80 */
{ PREGRP98 },
{ PREGRP99 },
- { "(bad)", { XX } },
+ { PREGRP107 },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
@@ -2876,11 +2948,11 @@ static const struct dis386 three_byte_ta
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREGRP100 },
+ { PREGRP101 },
+ { PREGRP102 },
+ { PREGRP103 },
+ { PREGRP104 },
/* e0 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
@@ -2997,7 +3069,7 @@ static const struct dis386 three_byte_ta
{ PREGRP84 },
{ PREGRP85 },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREGRP106 },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
@@ -3171,7 +3243,7 @@ static const struct dis386 three_byte_ta
{ "(bad)", { XX } },
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "(bad)", { XX } },
+ { PREGRP105 },
/* e0 */
{ "(bad)", { XX } },
{ "(bad)", { XX } },
@@ -6366,14 +6438,22 @@ VMX_Fixup (int extrachar ATTRIBUTE_UNUSE
static void
OP_VMX (int bytemode, int sizeflag)
{
- used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
- if (prefixes & PREFIX_DATA)
- strcpy (obuf, "vmclear");
- else if (prefixes & PREFIX_REPZ)
- strcpy (obuf, "vmxon");
+ if (modrm.mod == 3)
+ {
+ strcpy (obuf, "rdrand");
+ OP_E (v_mode, sizeflag);
+ }
else
- strcpy (obuf, "vmptrld");
- OP_E (bytemode, sizeflag);
+ {
+ used_prefixes |= (prefixes & (PREFIX_DATA | PREFIX_REPZ));
+ if (prefixes & PREFIX_DATA)
+ strcpy (obuf, "vmclear");
+ else if (prefixes & PREFIX_REPZ)
+ strcpy (obuf, "vmxon");
+ else
+ strcpy (obuf, "vmptrld");
+ OP_E (bytemode, sizeflag);
+ }
}
static void
Modified: stable/9/contrib/binutils/opcodes/i386-opc.h
==============================================================================
--- stable/9/contrib/binutils/opcodes/i386-opc.h Mon Oct 14 12:11:19 2013 (r256442)
+++ stable/9/contrib/binutils/opcodes/i386-opc.h Mon Oct 14 15:06:47 2013 (r256443)
@@ -72,19 +72,23 @@ typedef struct template
#define CpuSSE4_1 0x400000 /* SSE4.1 Instructions required */
#define CpuSSE4_2 0x800000 /* SSE4.2 Instructions required */
#define CpuXSAVE 0x1000000 /* XSAVE Instructions required */
-
-/* SSE4.1/4.2 Instructions required */
-#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
+#define CpuAES 0x2000000 /* AES Instructions required */
/* These flags are set by gas depending on the flag_code. */
#define Cpu64 0x4000000 /* 64bit support required */
#define CpuNo64 0x8000000 /* Not supported in the 64bit mode */
+#define CpuPCLMUL 0x10000000 /* Carry-less Multiplication extensions */
+#define CpuRdRnd 0x20000000 /* Intel Random Number Generator extensions */
+
+/* SSE4.1/4.2 Instructions required */
+#define CpuSSE4 (CpuSSE4_1|CpuSSE4_2)
+
/* The default value for unknown CPUs - enable all features to avoid problems. */
#define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
- |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE)
+ |CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd)
/* the bits in opcode_modifier are used to generate the final opcode from
the base_opcode. These bits also are used to detect alternate forms of
@@ -126,6 +130,8 @@ typedef struct template
#define Rex64 0x10000000 /* instruction require Rex64 prefix. */
#define Ugh 0x20000000 /* deprecated fp insn, gets a warning */
+#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf)
+
/* operand_types[i] describes the type of operand i. This is made
by OR'ing together all of the possible type masks. (e.g.
'operand_types[i] = Reg|Imm' specifies that operand i can be
Modified: stable/9/contrib/binutils/opcodes/i386-opc.tbl
==============================================================================
--- stable/9/contrib/binutils/opcodes/i386-opc.tbl Mon Oct 14 12:11:19 2013 (r256442)
+++ stable/9/contrib/binutils/opcodes/i386-opc.tbl Mon Oct 14 15:06:47 2013 (r256443)
@@ -1498,3 +1498,25 @@ xsetbv, 0, 0xf01, 0xd1, CpuXSAVE, No_bSu
xsave, 1, 0xfae, 0x4, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
xsaveopt, 1, 0xfae, 0x6, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+
+// INVPCID
+invpcid, 2, 0x660f3882, None, CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
+invpcid, 2, 0x660f3882, None, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg64 }
+
+// Intel AES extensions
+aesdec, 2, 0x660f38de, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
+aesdeclast, 2, 0x660f38df, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
+aesenc, 2, 0x660f38dc, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
+aesenclast, 2, 0x660f38dd, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
+aesimc, 2, 0x660f38db, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { RegXMM|LLongMem, RegXMM }
+aeskeygenassist, 3, 0x660f3adf, None, CpuAES, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM }
+
+// Intel Carry-less Multiplication extensions
+pclmulqdq, 3, 0x660f3a44, None, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Imm8, RegXMM|LLongMem, RegXMM }
+pclmullqlqdq, 2, 0x660f3a44, 0x0, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
+pclmulhqlqdq, 2, 0x660f3a44, 0x1, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
+pclmullqhqdq, 2, 0x660f3a44, 0x10, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
+pclmulhqhqdq, 2, 0x660f3a44, 0x11, CpuPCLMUL, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { RegXMM|LLongMem, RegXMM }
+
+// Intel Random Number Generator extensions
+rdrand, 1, 0x0fc7, 0x6, CpuRdRnd, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf, { Reg16|Reg32|Reg64 }
Modified: stable/9/contrib/binutils/opcodes/i386-tbl.h
==============================================================================
--- stable/9/contrib/binutils/opcodes/i386-tbl.h Mon Oct 14 12:11:19 2013 (r256442)
+++ stable/9/contrib/binutils/opcodes/i386-tbl.h Mon Oct 14 15:06:47 2013 (r256443)
@@ -3641,6 +3641,14 @@ const template i386_optab[] =
Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S,
Reg64 } },
+ { "invpcid", 2, 0x660f3882, None, CpuNo64,
+ Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
+ { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
+ Reg32 } },
+ { "invpcid", 2, 0x660f3882, None, Cpu64,
+ Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_xSuf|NoRex64,
+ { BaseIndex|Disp8|Disp16|Disp32|Disp32S,
+ Reg64 } },
{ "vmcall", 0, 0xf01, 0xc1, CpuVMX,
No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt,
{ 0 } },
@@ -4319,6 +4327,59 @@ const template i386_optab[] =
{ "xrstor", 1, 0xfae, 0x5, CpuXSAVE,
Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf,
{ BaseIndex|Disp8|Disp16|Disp32|Disp32S } },
+ /* Intel AES extensions */
+ {"aesdec", 2, 0x660f38de, None, CpuAES,
+ Modrm|IgnoreSize|NoSuf,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"aesdeclast", 2, 0x660f38df, None, CpuAES,
+ Modrm|IgnoreSize|NoSuf,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"aesenc", 2, 0x660f38dc, None, CpuAES,
+ Modrm|IgnoreSize|NoSuf,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"aesenclast", 2, 0x660f38dd, None, CpuAES,
+ Modrm|IgnoreSize|NoSuf,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"aesimc", 2, 0x660f38db, None, CpuAES,
+ Modrm|IgnoreSize|NoSuf,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"aeskeygenassist", 3, 0x660f3adf, None, CpuAES,
+ Modrm|IgnoreSize|NoSuf,
+ { Imm8, RegXMM|LLongMem,
+ RegXMM } },
+
+ /* Intel Carry-less Multiplication extensions */
+ {"pclmulqdq", 3, 0x660f3a44, None, CpuPCLMUL,
+ Modrm|IgnoreSize|NoSuf,
+ { Imm8, RegXMM|LLongMem,
+ RegXMM } },
+ {"pclmullqlqdq", 2, 0x660f3a44, 0x0, CpuPCLMUL,
+ Modrm|IgnoreSize|NoSuf|ImmExt,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"pclmulhqlqdq", 2, 0x660f3a44, 0x1, CpuPCLMUL,
+ Modrm|IgnoreSize|NoSuf|ImmExt,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"pclmullqhqdq", 2, 0x660f3a44, 0x10, CpuPCLMUL,
+ Modrm|IgnoreSize|NoSuf|ImmExt,
+ { RegXMM|LLongMem,
+ RegXMM } },
+ {"pclmulhqhqdq", 2, 0x660f3a44, 0x11, CpuPCLMUL,
+ Modrm|IgnoreSize|NoSuf|ImmExt,
+ { RegXMM|LLongMem,
+ RegXMM } },
+
+ /* Intel Random Number Generator extensions */
+ {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
+ Modrm|NoSuf,
+ { Reg16|Reg32|Reg64 } },
+
{ NULL, 0, 0, 0, 0, 0, { 0 } }
};
Modified: stable/9/sys/amd64/amd64/db_disasm.c
==============================================================================
--- stable/9/sys/amd64/amd64/db_disasm.c Mon Oct 14 12:11:19 2013 (r256442)
+++ stable/9/sys/amd64/amd64/db_disasm.c Mon Oct 14 15:06:47 2013 (r256443)
@@ -127,7 +127,7 @@ struct finst {
static const struct inst db_inst_0f388x[] = {
/*80*/ { "", TRUE, SDEP, op2(E, Rq), "invept" },
/*81*/ { "", TRUE, SDEP, op2(E, Rq), "invvpid" },
-/*82*/ { "", FALSE, NONE, 0, 0 },
+/*82*/ { "", TRUE, SDEP, op2(E, Rq), "invpcid" },
/*83*/ { "", FALSE, NONE, 0, 0 },
/*84*/ { "", FALSE, NONE, 0, 0 },
/*85*/ { "", FALSE, NONE, 0, 0 },
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