svn commit: r273203 - in projects/bhyve_svm: sys/amd64/vmm usr.sbin/bhyve

[Neel Natu]

Author: neel
Date: Fri Oct 17 03:04:38 2014
New Revision: 273203
URL: https://svnweb.freebsd.org/changeset/base/273203

Log:
  Hide extended PerfCtr MSRs on AMD processors by clearing bits 23, 24 and 28 in
  CPUID.80000001H:ECX.
  
  Handle accesses to PerfCtrX and PerfEvtSelX MSRs by ignoring writes and
  returning 0 on reads.
  
  This further reduces the number of unimplemented MSRs hit by a Linux guest
  during boot.

Modified:
  projects/bhyve_svm/sys/amd64/vmm/x86.c
  projects/bhyve_svm/usr.sbin/bhyve/xmsr.c

Modified: projects/bhyve_svm/sys/amd64/vmm/x86.c
==============================================================================
--- projects/bhyve_svm/sys/amd64/vmm/x86.c	Fri Oct 17 02:11:09 2014	(r273202)
+++ projects/bhyve_svm/sys/amd64/vmm/x86.c	Fri Oct 17 03:04:38 2014	(r273203)
@@ -159,6 +159,14 @@ x86_emulate_cpuid(struct vm *vm, int vcp
 			regs[2] &= ~(AMDID2_SVM | AMDID2_TOPOLOGY);
 
 			/*
+			 * Don't advertise extended performance counter MSRs
+			 * to the guest.
+			 */
+			regs[2] &= ~AMDID2_PCXC;
+			regs[2] &= ~AMDID2_PNXC;
+			regs[2] &= ~AMDID2_PTSCEL2I;
+
+			/*
 			 * Hide rdtscp/ia32_tsc_aux until we know how
 			 * to deal with them.
 			 */

Modified: projects/bhyve_svm/usr.sbin/bhyve/xmsr.c
==============================================================================
--- projects/bhyve_svm/usr.sbin/bhyve/xmsr.c	Fri Oct 17 02:11:09 2014	(r273202)
+++ projects/bhyve_svm/usr.sbin/bhyve/xmsr.c	Fri Oct 17 03:04:38 2014	(r273203)
@@ -68,6 +68,21 @@ emulate_wrmsr(struct vmctx *ctx, int vcp
 			 * Ignore writes to hardware configuration MSR.
 			 */
 			return (0);
+
+		case MSR_PERFEVSEL0:
+		case MSR_PERFEVSEL1:
+		case MSR_PERFEVSEL2:
+		case MSR_PERFEVSEL3:
+			/* Ignore writes to the PerfEvtSel MSRs */
+			return (0);
+
+		case MSR_K7_PERFCTR0:
+		case MSR_K7_PERFCTR1:
+		case MSR_K7_PERFCTR2:
+		case MSR_K7_PERFCTR3:
+			/* Ignore writes to the PerfCtr MSRs */
+			return (0);
+
 		default:
 			break;
 		}
@@ -111,6 +126,28 @@ emulate_rdmsr(struct vmctx *ctx, int vcp
 			*val = 0x01000010;	/* Reset value */
 			*val |= 1 << 9;		/* MONITOR/MWAIT disable */
 			break;
+
+		case MSR_PERFEVSEL0:
+		case MSR_PERFEVSEL1:
+		case MSR_PERFEVSEL2:
+		case MSR_PERFEVSEL3:
+			/*
+			 * PerfEvtSel MSRs are not properly virtualized so just
+			 * return zero.
+			 */
+			*val = 0;
+			break;
+
+		case MSR_K7_PERFCTR0:
+		case MSR_K7_PERFCTR1:
+		case MSR_K7_PERFCTR2:
+		case MSR_K7_PERFCTR3:
+			/*
+			 * PerfCtr MSRs are not properly virtualized so just
+			 * return zero.
+			 */
+			*val = 0;
+			break;
 		default:
 			break;
 		}