svn commit: r255679 - in projects/bhyve_npt_pmap/sys/amd64: amd64 include
Neel Natu
neel at FreeBSD.org
Wed Sep 18 22:26:43 UTC 2013
Author: neel
Date: Wed Sep 18 22:26:41 2013
New Revision: 255679
URL: http://svnweb.freebsd.org/changeset/base/255679
Log:
Move the nested PTE bit definitions to pmap.h.
Redefine the PG_xx macros that implicitly refer to bits in the x86 PTEs
to now refer to them explicitly.
Allow code that deals with both regular and nested page table entries to be
compiled with a select set of PG_xx macros undefined. This happens because
the PG_xx macros define bits that are located at different positions in
x86 and nested PTEs. The appropriate bitmask will be determined at runtime
depending on the pmap type.
Requested by: kib@
Modified:
projects/bhyve_npt_pmap/sys/amd64/amd64/machdep.c
projects/bhyve_npt_pmap/sys/amd64/amd64/pmap.c
projects/bhyve_npt_pmap/sys/amd64/include/pmap.h
Modified: projects/bhyve_npt_pmap/sys/amd64/amd64/machdep.c
==============================================================================
--- projects/bhyve_npt_pmap/sys/amd64/amd64/machdep.c Wed Sep 18 21:15:21 2013 (r255678)
+++ projects/bhyve_npt_pmap/sys/amd64/amd64/machdep.c Wed Sep 18 22:26:41 2013 (r255679)
@@ -1574,7 +1574,7 @@ getmemsize(caddr_t kmdp, u_int64_t first
/*
* map page into kernel: valid, read/write,non-cacheable
*/
- *pte = pa | PG_V | PG_RW | PG_N;
+ *pte = pa | PG_V | PG_RW | PG_NC_PWT | PG_NC_PCD;
invltlb();
tmp = *(int *)ptr;
Modified: projects/bhyve_npt_pmap/sys/amd64/amd64/pmap.c
==============================================================================
--- projects/bhyve_npt_pmap/sys/amd64/amd64/pmap.c Wed Sep 18 21:15:21 2013 (r255678)
+++ projects/bhyve_npt_pmap/sys/amd64/amd64/pmap.c Wed Sep 18 22:26:41 2013 (r255679)
@@ -76,6 +76,8 @@
* SUCH DAMAGE.
*/
+#define AMD64_NPT_AWARE
+
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
@@ -143,28 +145,6 @@ __FBSDID("$FreeBSD$");
#include <machine/smp.h>
#endif
-/* Intel EPT bits */
-#define EPT_PG_RD (1 << 0)
-#define EPT_PG_WR (1 << 1)
-#define EPT_PG_EX (1 << 2)
-#define EPT_PG_MEMORY_TYPE(x) ((x) << 3)
-#define EPT_PG_IGNORE_PAT (1 << 6)
-#define EPT_PG_PS (1 << 7)
-#define EPT_PG_A (1 << 8)
-#define EPT_PG_M (1 << 9)
-
-/*
- * undef the PG_xx macros that define bits in the regular x86 PTEs that have
- * a different position in nested PTEs.
- *
- * The appropriate bitmask is now calculated at runtime based on the pmap
- * type.
- */
-
-#undef PG_AVAIL1 /* PG_AVAIL1 aliases with EPT_PG_M */
-
-#undef PG_G
-#define X86_PG_G 0x100
static __inline pt_entry_t
pmap_global_bit(pmap_t pmap)
{
@@ -184,8 +164,6 @@ pmap_global_bit(pmap_t pmap)
return (mask);
}
-#undef PG_A
-#define X86_PG_A 0x020
static __inline pt_entry_t
pmap_accessed_bit(pmap_t pmap)
{
@@ -205,8 +183,6 @@ pmap_accessed_bit(pmap_t pmap)
return (mask);
}
-#undef PG_M
-#define X86_PG_M 0x040
static __inline pt_entry_t
pmap_modified_bit(pmap_t pmap)
{
@@ -226,18 +202,6 @@ pmap_modified_bit(pmap_t pmap)
return (mask);
}
-#undef PG_PDE_PAT
-#define X86_PG_PDE_PAT 0x1000
-
-#undef PG_PDE_CACHE
-#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | PG_NC_PWT | PG_NC_PCD)
-
-#undef PG_PTE_PAT
-#define X86_PG_PTE_PAT 0x080
-
-#undef PG_PTE_CACHE
-#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | PG_NC_PWT | PG_NC_PCD)
-
#if !defined(DIAGNOSTIC)
#ifdef __GNUC_GNU_INLINE__
#define PMAP_INLINE __attribute__((__gnu_inline__)) inline
Modified: projects/bhyve_npt_pmap/sys/amd64/include/pmap.h
==============================================================================
--- projects/bhyve_npt_pmap/sys/amd64/include/pmap.h Wed Sep 18 21:15:21 2013 (r255678)
+++ projects/bhyve_npt_pmap/sys/amd64/include/pmap.h Wed Sep 18 22:26:41 2013 (r255679)
@@ -50,34 +50,64 @@
* of the fields not present here and there, depending on a lot of things.
*/
/* ---- Intel Nomenclature ---- */
-#define PG_V 0x001 /* P Valid */
-#define PG_RW 0x002 /* R/W Read/Write */
-#define PG_U 0x004 /* U/S User/Supervisor */
-#define PG_NC_PWT 0x008 /* PWT Write through */
-#define PG_NC_PCD 0x010 /* PCD Cache disable */
-#define PG_A 0x020 /* A Accessed */
-#define PG_M 0x040 /* D Dirty */
-#define PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
-#define PG_PTE_PAT 0x080 /* PAT PAT index */
-#define PG_G 0x100 /* G Global */
-#define PG_AVAIL1 0x200 /* / Available for system */
-#define PG_AVAIL2 0x400 /* < programmers use */
-#define PG_AVAIL3 0x800 /* \ */
-#define PG_PDE_PAT 0x1000 /* PAT PAT index */
-#define PG_NX (1ul<<63) /* No-execute */
+#define X86_PG_V 0x001 /* P Valid */
+#define X86_PG_RW 0x002 /* R/W Read/Write */
+#define X86_PG_U 0x004 /* U/S User/Supervisor */
+#define X86_PG_NC_PWT 0x008 /* PWT Write through */
+#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */
+#define X86_PG_A 0x020 /* A Accessed */
+#define X86_PG_M 0x040 /* D Dirty */
+#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
+#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
+#define X86_PG_G 0x100 /* G Global */
+#define X86_PG_AVAIL1 0x200 /* / Available for system */
+#define X86_PG_AVAIL2 0x400 /* < programmers use */
+#define X86_PG_AVAIL3 0x800 /* \ */
+#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */
+#define X86_PG_NX (1ul<<63) /* No-execute */
+
+/* Page level cache control fields used to determine the PAT type */
+#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
+#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
/*
- * PG_AVAIL1 is available for software use only with the regular x86 PTEs.
- * PG_AVAIL2 and PG_AVAIL3 are available in both the regular and nested PTEs.
+ * Intel extended page table (EPT) bit definitions.
*/
+#define EPT_PG_RD 0x001 /* R Read */
+#define EPT_PG_WR 0x002 /* W Write */
+#define EPT_PG_EX 0x004 /* X Execute */
+#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */
+#define EPT_PG_PS 0x080 /* PS Page size */
+#define EPT_PG_A 0x100 /* A Accessed */
+#define EPT_PG_M 0x200 /* D Dirty */
+#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */
+
+/*
+ * Define the PG_xx macros in terms of the bits on x86 PTEs.
+ */
+#define PG_V X86_PG_V
+#define PG_RW X86_PG_RW
+#define PG_U X86_PG_U
+#define PG_NC_PWT X86_PG_NC_PWT
+#define PG_NC_PCD X86_PG_NC_PCD
+#define PG_A X86_PG_A
+#define PG_M X86_PG_M
+#define PG_PS X86_PG_PS
+#define PG_PTE_PAT X86_PG_PTE_PAT
+#define PG_G X86_PG_G
+#define PG_AVAIL1 X86_PG_AVAIL1
+#define PG_AVAIL2 X86_PG_AVAIL2
+#define PG_AVAIL3 X86_PG_AVAIL3
+#define PG_PDE_PAT X86_PG_PDE_PAT
+#define PG_NX X86_PG_NX
+#define PG_PDE_CACHE X86_PG_PDE_CACHE
+#define PG_PTE_CACHE X86_PG_PTE_CACHE
/* Our various interpretations of the above */
#define PG_W PG_AVAIL3 /* "Wired" pseudoflag */
#define PG_MANAGED PG_AVAIL2
#define PG_FRAME (0x000ffffffffff000ul)
#define PG_PS_FRAME (0x000fffffffe00000ul)
-#define PG_PROT (PG_RW|PG_U) /* all protection bits . */
-#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */
/*
* "readonly" pseudo-flag used in pmap entries that require software emulation
@@ -85,10 +115,6 @@
*/
#define PG_RO (1ul << 52)
-/* Page level cache control fields used to determine the PAT type */
-#define PG_PDE_CACHE (PG_PDE_PAT | PG_NC_PWT | PG_NC_PCD)
-#define PG_PTE_CACHE (PG_PTE_PAT | PG_NC_PWT | PG_NC_PCD)
-
/*
* Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
* (PTE) page mappings have identical settings for the following fields:
@@ -106,6 +132,26 @@
#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
#define PGEX_I 0x10 /* during an instruction fetch */
+/*
+ * undef the PG_xx macros that define bits in the regular x86 PTEs that
+ * have a different position in nested PTEs. This is done when compiling
+ * code that needs to be aware of the differences between regular x86 and
+ * nested PTEs.
+ *
+ * The appropriate bitmask will be calculated at runtime based on the pmap
+ * type.
+ */
+#ifdef AMD64_NPT_AWARE
+#undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */
+#undef PG_G
+#undef PG_A
+#undef PG_M
+#undef PG_PDE_PAT
+#undef PG_PDE_CACHE
+#undef PG_PTE_PAT
+#undef PG_PTE_CACHE
+#endif
+
/*
* Pte related macros. This is complicated by having to deal with
* the sign extension of the 48th bit.
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