svn commit: r230911 - projects/armv6/sys/arm/arm
Grzegorz Bernacki
gber at FreeBSD.org
Thu Feb 2 12:22:22 UTC 2012
Author: gber
Date: Thu Feb 2 12:22:22 2012
New Revision: 230911
URL: http://svn.freebsd.org/changeset/base/230911
Log:
Fix getting cache level of coherency and remove Marvell specific code.
Submitted by: Damjan Marion
Modified:
projects/armv6/sys/arm/arm/cpufunc.c
projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S
Modified: projects/armv6/sys/arm/arm/cpufunc.c
==============================================================================
--- projects/armv6/sys/arm/arm/cpufunc.c Thu Feb 2 11:18:34 2012 (r230910)
+++ projects/armv6/sys/arm/arm/cpufunc.c Thu Feb 2 12:22:22 2012 (r230911)
@@ -1083,7 +1083,7 @@ get_cachetype_cp15()
__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
: "=r" (clevel));
arm_cache_level = clevel;
- arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level) + 1;
+ arm_cache_loc = CPU_CLIDR_LOC(arm_cache_level);
i = 0;
while ((type = (clevel & 0x7)) && i < 7) {
if (type == CACHE_DCACHE || type == CACHE_UNI_CACHE ||
Modified: projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S
==============================================================================
--- projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S Thu Feb 2 11:18:34 2012 (r230910)
+++ projects/armv6/sys/arm/arm/cpufunc_asm_armv7.S Thu Feb 2 12:22:22 2012 (r230911)
@@ -97,6 +97,7 @@ ENTRY(armv7_dcache_wbinv_all)
Loop1:
/* Get cache type for given level */
mov r2, r8, lsl #2
+ add r2, r2, r2
ldr r0, .Lcache_type
ldr r1, [r0, r2]
@@ -131,7 +132,6 @@ Skip:
bne Loop1
Finished:
isb
- mcr p15, 0, r0, c7, c5, 5
ldmia sp!, {r4, r5, r6, r7, r8, r9}
RET
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