svn commit: r198160 - projects/mips/sys/mips/rmi
Randall Stewart
rrs at FreeBSD.org
Thu Oct 15 21:14:42 UTC 2009
Author: rrs
Date: Thu Oct 15 21:14:42 2009
New Revision: 198160
URL: http://svn.freebsd.org/changeset/base/198160
Log:
More initial RMI files. Note that these so far do NOT
compile and many of them may disappear. For example
the xlr_boot1_console.c is old code that is ifdef'd out.
I will clean these sorts of things up as I make progress
on the port. So far the only thing I have I think straightened
out is the bits around the interupt handling... and hey that
may be broke ;-)
Added:
projects/mips/sys/mips/rmi/Makefile.msgring
projects/mips/sys/mips/rmi/board.c
projects/mips/sys/mips/rmi/board.h
projects/mips/sys/mips/rmi/clock.c
projects/mips/sys/mips/rmi/clock.h
projects/mips/sys/mips/rmi/debug.h (contents, props changed)
projects/mips/sys/mips/rmi/interrupt.h
projects/mips/sys/mips/rmi/iodi.c
projects/mips/sys/mips/rmi/iomap.h
projects/mips/sys/mips/rmi/msgring.c
projects/mips/sys/mips/rmi/msgring.cfg
projects/mips/sys/mips/rmi/msgring.h (contents, props changed)
projects/mips/sys/mips/rmi/msgring_xls.c
projects/mips/sys/mips/rmi/msgring_xls.cfg (contents, props changed)
projects/mips/sys/mips/rmi/on_chip.c
projects/mips/sys/mips/rmi/pcibus.c
projects/mips/sys/mips/rmi/pcibus.h
projects/mips/sys/mips/rmi/perfmon.h
projects/mips/sys/mips/rmi/perfmon_kern.c
projects/mips/sys/mips/rmi/perfmon_percpu.c
projects/mips/sys/mips/rmi/perfmon_utils.h
projects/mips/sys/mips/rmi/perfmon_xlrconfig.h
projects/mips/sys/mips/rmi/pic.h
projects/mips/sys/mips/rmi/shared_structs.h (contents, props changed)
projects/mips/sys/mips/rmi/shared_structs_func.h (contents, props changed)
projects/mips/sys/mips/rmi/shared_structs_offsets.h (contents, props changed)
projects/mips/sys/mips/rmi/uart_bus_xlr_iodi.c
projects/mips/sys/mips/rmi/uart_cpu_mips_xlr.c
projects/mips/sys/mips/rmi/xlr_boot1_console.c
projects/mips/sys/mips/rmi/xlr_csum_nocopy.S
projects/mips/sys/mips/rmi/xlr_i2c.c
projects/mips/sys/mips/rmi/xlr_machdep.c
projects/mips/sys/mips/rmi/xlr_pci.c
projects/mips/sys/mips/rmi/xlrconfig.h
projects/mips/sys/mips/rmi/xls_ehci.c
Added: projects/mips/sys/mips/rmi/Makefile.msgring
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/Makefile.msgring Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,14 @@
+RM = rm
+MSGRNG_CFG = msgring.cfg
+
+MSGRNG_CFG_C = $(patsubst %.cfg,%.c,$(MSGRNG_CFG))
+
+#all: msgring.l msgring.y msgring.cfg
+all: $(MSGRNG_CFG)
+ flex -omsgring.lex.c msgring.l
+ bison -d -omsgring.yacc.c msgring.y
+ gcc -g3 msgring.lex.c msgring.yacc.c -o msgring
+ ./msgring -i $(MSGRNG_CFG) -o $(MSGRNG_CFG_C)
+
+clean:
+ $(RM) -f msgring.lex.c msgring.yacc.c msgring.yacc.h msgring msgring.o*
Added: projects/mips/sys/mips/rmi/board.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/board.c Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,178 @@
+/*********************************************************************
+ *
+ * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
+ * reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * *****************************RMI_2**********************************/
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <machine/cpufunc.h>
+#include <mips/xlr/msgring.h>
+#include <mips/xlr/board.h>
+#include <mips/xlr/pic.h>
+
+static int xlr_rxstn_to_txstn_map[128] = {
+ [0 ... 7] = TX_STN_CPU_0,
+ [8 ... 15] = TX_STN_CPU_1,
+ [16 ... 23] = TX_STN_CPU_2,
+ [24 ... 31] = TX_STN_CPU_3,
+ [32 ... 39] = TX_STN_CPU_4,
+ [40 ... 47] = TX_STN_CPU_5,
+ [48 ... 55] = TX_STN_CPU_6,
+ [56 ... 63] = TX_STN_CPU_7,
+ [64 ... 95] = TX_STN_INVALID,
+ [96 ... 103] = TX_STN_GMAC,
+ [104 ... 107] = TX_STN_DMA,
+ [108 ... 111] = TX_STN_INVALID,
+ [112 ... 113] = TX_STN_XGS_0,
+ [114 ... 115] = TX_STN_XGS_1,
+ [116 ... 119] = TX_STN_INVALID,
+ [120 ... 127] = TX_STN_SAE
+};
+
+static int xls_rxstn_to_txstn_map[128] = {
+ [0 ... 7] = TX_STN_CPU_0,
+ [8 ... 15] = TX_STN_CPU_1,
+ [16 ... 23] = TX_STN_CPU_2,
+ [24 ... 31] = TX_STN_CPU_3,
+ [32 ... 63] = TX_STN_INVALID,
+ [64 ... 71] = TX_STN_PCIE,
+ [72 ... 79] = TX_STN_INVALID,
+ [80 ... 87] = TX_STN_GMAC1,
+ [88 ... 95] = TX_STN_INVALID,
+ [96 ... 103] = TX_STN_GMAC0,
+ [104 ... 107] = TX_STN_DMA,
+ [108 ... 111] = TX_STN_CDE,
+ [112 ... 119] = TX_STN_INVALID,
+ [120 ... 127] = TX_STN_SAE
+};
+
+struct stn_cc *xlr_core_cc_configs[] = {&cc_table_cpu_0, &cc_table_cpu_1,
+ &cc_table_cpu_2, &cc_table_cpu_3,
+ &cc_table_cpu_4, &cc_table_cpu_5,
+ &cc_table_cpu_6, &cc_table_cpu_7 };
+
+struct stn_cc *xls_core_cc_configs[] = {&xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
+ &xls_cc_table_cpu_2, &xls_cc_table_cpu_3};
+
+struct xlr_board_info xlr_board_info;
+
+/*
+ * All our knowledge of chip and board that cannot be detected by probing
+ * at run-time goes here
+ */
+int xlr_board_info_setup()
+{
+ if (xlr_is_xls()) {
+ xlr_board_info.is_xls = 1;
+ xlr_board_info.nr_cpus = 8;
+ xlr_board_info.usb = 1;
+ xlr_board_info.cfi =
+ (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
+ xlr_board_info.pci_irq = 0;
+ xlr_board_info.credit_configs = xls_core_cc_configs;
+ xlr_board_info.bucket_sizes = &xls_bucket_sizes;
+ xlr_board_info.msgmap = xls_rxstn_to_txstn_map;
+ xlr_board_info.gmacports = 8;
+
+ /* network block 0 */
+ xlr_board_info.gmac_block[0].type = XLR_GMAC;
+ xlr_board_info.gmac_block[0].enabled = 0xf;
+ xlr_board_info.gmac_block[0].credit_config = &xls_cc_table_gmac0;
+ xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
+ xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
+ if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI)
+ xlr_board_info.gmac_block[0].mode = XLR_PORT0_RGMII;
+ else
+ xlr_board_info.gmac_block[0].mode = XLR_SGMII;
+ xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
+ xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
+ xlr_board_info.gmac_block[0].baseinst = 0;
+
+ /* network block 1 */
+ xlr_board_info.gmac_block[1].type = XLR_GMAC;
+ xlr_board_info.gmac_block[1].enabled = 0xf;
+ xlr_board_info.gmac_block[1].credit_config = &xls_cc_table_gmac1;
+ xlr_board_info.gmac_block[1].station_txbase = MSGRNG_STNID_GMAC1_TX0;
+ xlr_board_info.gmac_block[1].station_rfr = MSGRNG_STNID_GMAC1_FR_0;
+ xlr_board_info.gmac_block[1].mode = XLR_SGMII;
+ xlr_board_info.gmac_block[1].baseaddr = XLR_IO_GMAC_4_OFFSET;
+ xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
+ xlr_board_info.gmac_block[1].baseinst = 4;
+
+ /* network block 2 */
+ xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */
+ } else {
+ xlr_board_info.is_xls = 0;
+ xlr_board_info.nr_cpus = 32;
+ xlr_board_info.usb = 0;
+ xlr_board_info.cfi = 1;
+ xlr_board_info.pci_irq = 0;
+ xlr_board_info.credit_configs = xlr_core_cc_configs;
+ xlr_board_info.bucket_sizes = &bucket_sizes;
+ xlr_board_info.msgmap = xlr_rxstn_to_txstn_map;
+ xlr_board_info.gmacports = 4;
+
+ /* GMAC0 */
+ xlr_board_info.gmac_block[0].type = XLR_GMAC;
+ xlr_board_info.gmac_block[0].enabled = 0xf;
+ xlr_board_info.gmac_block[0].credit_config = &cc_table_gmac;
+ xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
+ xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
+ xlr_board_info.gmac_block[0].mode = XLR_RGMII;
+ xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
+ xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
+ xlr_board_info.gmac_block[0].baseinst = 0;
+
+ /* XGMAC0 */
+ xlr_board_info.gmac_block[1].type = XLR_XGMAC;
+ xlr_board_info.gmac_block[1].enabled = 1;
+ xlr_board_info.gmac_block[1].credit_config = &cc_table_xgs_0;
+ xlr_board_info.gmac_block[1].station_txbase = MSGRNG_STNID_XGS0_TX;
+ xlr_board_info.gmac_block[1].station_rfr = MSGRNG_STNID_XGS0FR;
+ xlr_board_info.gmac_block[1].mode = -1;
+ xlr_board_info.gmac_block[1].baseaddr = XLR_IO_XGMAC_0_OFFSET;
+ xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
+ xlr_board_info.gmac_block[1].baseinst = 4;
+
+ /* XGMAC1 */
+ xlr_board_info.gmac_block[2].type = XLR_XGMAC;
+ xlr_board_info.gmac_block[2].enabled = 1;
+ xlr_board_info.gmac_block[2].credit_config = &cc_table_xgs_1;
+ xlr_board_info.gmac_block[2].station_txbase = MSGRNG_STNID_XGS1_TX;
+ xlr_board_info.gmac_block[2].station_rfr = MSGRNG_STNID_XGS1FR;
+ xlr_board_info.gmac_block[2].mode = -1;
+ xlr_board_info.gmac_block[2].baseaddr = XLR_IO_XGMAC_1_OFFSET;
+ xlr_board_info.gmac_block[2].baseirq = PIC_XGS_1_IRQ;
+ xlr_board_info.gmac_block[2].baseinst = 5;
+ }
+ return 0;
+}
Added: projects/mips/sys/mips/rmi/board.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/board.h Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,275 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _RMI_BOARD_H_
+#define _RMI_BOARD_H_
+
+#define RMI_XLR_BOARD_ARIZONA_I 1
+#define RMI_XLR_BOARD_ARIZONA_II 2
+#define RMI_XLR_BOARD_ARIZONA_III 3
+#define RMI_XLR_BOARD_ARIZONA_IV 4
+#define RMI_XLR_BOARD_ARIZONA_V 5
+#define RMI_XLR_BOARD_ARIZONA_VI 6
+#define RMI_XLR_BOARD_ARIZONA_VII 7
+#define RMI_XLR_BOARD_ARIZONA_VIII 8
+
+#define RMI_CHIP_XLR308_A0 0x0c0600
+#define RMI_CHIP_XLR508_A0 0x0c0700
+#define RMI_CHIP_XLR516_A0 0x0c0800
+#define RMI_CHIP_XLR532_A0 0x0c0900
+#define RMI_CHIP_XLR716_A0 0x0c0a00
+#define RMI_CHIP_XLR732_A0 0x0c0b00
+
+#define RMI_CHIP_XLR308_A1 0x0c0601
+#define RMI_CHIP_XLR508_A1 0x0c0701
+#define RMI_CHIP_XLR516_A1 0x0c0801
+#define RMI_CHIP_XLR532_A1 0x0c0901
+#define RMI_CHIP_XLR716_A1 0x0c0a01
+#define RMI_CHIP_XLR732_A1 0x0c0b01
+
+#define RMI_CHIP_XLR308_B0 0x0c0602
+#define RMI_CHIP_XLR508_B0 0x0c0702
+#define RMI_CHIP_XLR516_B0 0x0c0802
+#define RMI_CHIP_XLR532_B0 0x0c0902
+#define RMI_CHIP_XLR716_B0 0x0c0a02
+#define RMI_CHIP_XLR732_B0 0x0c0b02
+
+#define RMI_CHIP_XLR308_B1 0x0c0603
+#define RMI_CHIP_XLR508_B1 0x0c0703
+#define RMI_CHIP_XLR516_B1 0x0c0803
+#define RMI_CHIP_XLR532_B1 0x0c0903
+#define RMI_CHIP_XLR716_B1 0x0c0a03
+#define RMI_CHIP_XLR732_B1 0x0c0b03
+
+#define RMI_CHIP_XLR308_B2 0x0c0604
+#define RMI_CHIP_XLR508_B2 0x0c0704
+#define RMI_CHIP_XLR516_B2 0x0c0804
+#define RMI_CHIP_XLR532_B2 0x0c0904
+#define RMI_CHIP_XLR716_B2 0x0c0a04
+#define RMI_CHIP_XLR732_B2 0x0c0b04
+
+#define RMI_CHIP_XLR308_C0 0x0c0705
+#define RMI_CHIP_XLR508_C0 0x0c0b05
+#define RMI_CHIP_XLR516_C0 0x0c0a05
+#define RMI_CHIP_XLR532_C0 0x0c0805
+#define RMI_CHIP_XLR716_C0 0x0c0205
+#define RMI_CHIP_XLR732_C0 0x0c0005
+
+#define RMI_CHIP_XLR308_C1 0x0c0706
+#define RMI_CHIP_XLR508_C1 0x0c0b06
+#define RMI_CHIP_XLR516_C1 0x0c0a06
+#define RMI_CHIP_XLR532_C1 0x0c0806
+#define RMI_CHIP_XLR716_C1 0x0c0206
+#define RMI_CHIP_XLR732_C1 0x0c0006
+
+#define RMI_CHIP_XLR308_C2 0x0c0707
+#define RMI_CHIP_XLR508_C2 0x0c0b07
+#define RMI_CHIP_XLR516_C2 0x0c0a07
+#define RMI_CHIP_XLR532_C2 0x0c0807
+#define RMI_CHIP_XLR716_C2 0x0c0207
+#define RMI_CHIP_XLR732_C2 0x0c0007
+
+#define RMI_CHIP_XLR308_C3 0x0c0708
+#define RMI_CHIP_XLR508_C3 0x0c0b08
+#define RMI_CHIP_XLR516_C3 0x0c0a08
+#define RMI_CHIP_XLR532_C3 0x0c0808
+#define RMI_CHIP_XLR716_C3 0x0c0208
+#define RMI_CHIP_XLR732_C3 0x0c0008
+
+#define RMI_CHIP_XLR308_C4 0x0c0709
+#define RMI_CHIP_XLR508_C4 0x0c0b09
+#define RMI_CHIP_XLR516_C4 0x0c0a09
+#define RMI_CHIP_XLR532_C4 0x0c0809
+#define RMI_CHIP_XLR716_C4 0x0c0209
+#define RMI_CHIP_XLR732_C4 0x0c0009
+
+#define RMI_CHIP_XLS608_A0 0x0c8000
+#define RMI_CHIP_XLS408_A0 0x0c8800
+#define RMI_CHIP_XLS404_A0 0x0c8c00
+#define RMI_CHIP_XLS208_A0 0x0c8e00
+#define RMI_CHIP_XLS204_A0 0x0c8f00
+
+#define RMI_CHIP_XLS608_A1 0x0c8001
+#define RMI_CHIP_XLS408_A1 0x0c8801
+#define RMI_CHIP_XLS404_A1 0x0c8c01
+#define RMI_CHIP_XLS208_A1 0x0c8e01
+#define RMI_CHIP_XLS204_A1 0x0c8f01
+
+static __inline__ unsigned int
+xlr_revision(void)
+{
+ return mips_rd_prid() & 0xff00ff;
+}
+
+static __inline__ unsigned int
+xlr_is_xls(void)
+{
+ uint32_t prid = mips_rd_prid();
+
+ return (prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000;
+}
+
+static __inline__ int
+xlr_revision_a0(void)
+{
+ return xlr_revision() == 0x0c0000;
+}
+
+static __inline__ int
+xlr_revision_b0(void)
+{
+ return xlr_revision() == 0x0c0002;
+}
+
+static __inline__ int
+xlr_revision_b1(void)
+{
+ return xlr_revision() == 0x0c0003;
+}
+
+static __inline__ int
+xlr_board_atx_i(void)
+{
+ return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_I;
+}
+
+static __inline__ int
+xlr_board_atx_ii(void)
+{
+ return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_II;
+}
+
+static __inline__ int
+xlr_board_atx_ii_b(void)
+{
+ return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_II)
+ && (xlr_boot1_info.board_minor_version == 1);
+}
+
+static __inline__ int
+xlr_board_atx_iii(void)
+{
+ return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III;
+}
+
+static __inline__ int
+xlr_board_atx_iv(void)
+{
+ return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_IV)
+ && (xlr_boot1_info.board_minor_version == 0); }
+static __inline__ int
+xlr_board_atx_iv_b(void)
+{
+ return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_IV)
+ && (xlr_boot1_info.board_minor_version == 1);
+}
+static __inline__ int
+xlr_board_atx_v(void)
+{
+ return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_V;
+}
+static __inline__ int
+xlr_board_atx_vi(void)
+{
+ return xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI;
+}
+
+static __inline__ int
+xlr_board_atx_iii_256(void)
+{
+ return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III)
+ && (xlr_boot1_info.board_minor_version == 0);
+}
+
+static __inline__ int
+xlr_board_atx_iii_512(void)
+{
+ return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_III)
+ && (xlr_boot1_info.board_minor_version == 1);
+}
+
+static __inline__ int
+xlr_board_atx_v_512(void)
+{
+ return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_V)
+ && (xlr_boot1_info.board_minor_version == 1);
+}
+
+static __inline__ int
+xlr_board_pci(void)
+{
+ return (xlr_board_atx_iii_256() || xlr_board_atx_iii_512()
+ || xlr_board_atx_v_512());
+}
+static __inline__ int
+xlr_is_xls2xx(void)
+{
+ uint32_t chipid = mips_rd_prid() & 0xffffff00U;
+
+ return chipid == 0x0c8e00 || chipid == 0x0c8f00;
+}
+
+static __inline__ int
+xlr_is_xls4xx(void)
+{
+ uint32_t chipid = mips_rd_prid() & 0xffffff00U;
+
+ return chipid == 0x0c8800 || chipid == 0x0c8c00;
+}
+
+/* all our knowledge of chip and board that cannot be detected run-time goes here */
+enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
+enum gmac_block_modes { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII };
+struct xlr_board_info {
+ int is_xls;
+ int nr_cpus;
+ int usb; /* usb enabled ? */
+ int cfi; /* compact flash driver for NOR? */
+ int pci_irq;
+ struct stn_cc **credit_configs; /* pointer to Core station credits */
+ struct bucket_size *bucket_sizes; /* pointer to Core station bucket */
+ int *msgmap; /* mapping of message station to devices */
+ int gmacports; /* number of gmac ports on the board */
+ struct xlr_gmac_block_t {
+ int type; /* see enum gmac_block_types */
+ unsigned int enabled; /* mask of ports enabled */
+ struct stn_cc *credit_config; /* credit configuration */
+ int station_txbase; /* station id for tx */
+ int station_rfr; /* free desc bucket */
+ int mode; /* see gmac_block_modes */
+ uint32_t baseaddr; /* IO base */
+ int baseirq; /* first irq for this block, the rest are in sequence */
+ int baseinst; /* the first rge unit for this block */
+ } gmac_block [3];
+};
+
+extern struct xlr_board_info xlr_board_info;
+int xlr_board_info_setup(void);
+
+#endif
Added: projects/mips/sys/mips/rmi/clock.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/clock.c Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,213 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/queue.h>
+#include <sys/smp.h>
+#include <sys/sysctl.h>
+#include <sys/systm.h>
+#include <sys/timetc.h>
+
+#include <sys/module.h>
+#include <sys/stdint.h>
+
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/systm.h>
+#include <sys/clock.h>
+
+#include <machine/clock.h>
+#include <machine/md_var.h>
+#include <machine/hwfunc.h>
+#include <machine/intr_machdep.h>
+
+#include <mips/xlr/iomap.h>
+#include <mips/xlr/clock.h>
+#include <mips/xlr/interrupt.h>
+#include <mips/xlr/pic.h>
+#include <mips/xlr/shared_structs.h>
+
+#ifdef XLR_PERFMON
+#include <mips/xlr/perfmon.h>
+#endif
+
+int hw_clockrate;
+SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, &hw_clockrate,
+ 0, "CPU instruction clock rate");
+
+#define STAT_PROF_CLOCK_SCALE_FACTOR 8
+
+static int scale_factor;
+static int count_scale_factor[32];
+
+uint64_t platform_get_frequency()
+{
+ return XLR_PIC_HZ;
+}
+
+/*
+* count_compare_clockhandler:
+*
+* Handle the clock interrupt when count becomes equal to
+* compare.
+*/
+void
+count_compare_clockhandler(struct trapframe *tf)
+{
+ int cpu = PCPU_GET(cpuid);
+ uint32_t cycles;
+
+ critical_enter();
+
+ if (cpu == 0) {
+ mips_wr_compare(0);
+ }
+ else {
+ count_scale_factor[cpu]++;
+ cycles = mips_rd_count();
+ cycles += XLR_CPU_HZ/hz;
+ mips_wr_compare(cycles);
+
+ hardclock_process((struct clockframe *)tf);
+ if (count_scale_factor[cpu] == STAT_PROF_CLOCK_SCALE_FACTOR) {
+ statclock((struct clockframe *)tf);
+ if(profprocs != 0) {
+ profclock((struct clockframe *)tf);
+ }
+ count_scale_factor[cpu] = 0;
+ }
+
+ /* If needed , handle count compare tick skew here */
+ }
+
+ critical_exit();
+}
+
+void
+pic_hardclockhandler(struct trapframe *tf)
+{
+ int cpu = PCPU_GET(cpuid);
+
+ critical_enter();
+
+ if (cpu == 0) {
+ scale_factor++;
+ hardclock((struct clockframe *)tf);
+ if (scale_factor == STAT_PROF_CLOCK_SCALE_FACTOR) {
+ statclock((struct clockframe *)tf);
+ if(profprocs != 0) {
+ profclock((struct clockframe *)tf);
+ }
+ scale_factor = 0;
+ }
+#ifdef XLR_PERFMON
+ if (xlr_perfmon_started)
+ xlr_perfmon_clockhandler();
+#endif
+
+ }
+ else {
+ /* If needed , handle count compare tick skew here */
+ }
+
+ critical_exit();
+}
+
+void
+pic_timecounthandler(struct trapframe *tf)
+{
+}
+
+void
+platform_initclocks(void)
+{
+ int cpu = PCPU_GET(cpuid);
+ void *cookie;
+
+ /* Note: Passing #3 as NULL ensures that clockhandler
+ * gets called with trapframe
+ */
+ /* profiling/process accounting timer interrupt for non-zero cpus */
+ cpu_establish_intr("compare", IRQ_TIMER,
+ (driver_intr_t *)count_compare_clockhandler,
+ NULL, INTR_TYPE_CLK|INTR_FAST, &cookie, NULL, NULL);
+
+ /* timekeeping timer interrupt for cpu 0 */
+ cpu_establish_intr("hardclk", PIC_TIMER_7_IRQ,
+ (driver_intr_t *)pic_hardclockhandler,
+ NULL, INTR_TYPE_CLK|INTR_FAST, &cookie, NULL, NULL);
+
+ /* this is used by timecounter */
+ cpu_establish_intr("timecount", PIC_TIMER_6_IRQ,
+ (driver_intr_t *)pic_timecounthandler,
+ NULL, INTR_TYPE_CLK|INTR_FAST, &cookie, NULL, NULL);
+
+ if (cpu == 0) {
+ __uint64_t maxval = XLR_PIC_HZ/hz;
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
+ profhz = stathz;
+
+ /* Setup PIC Interrupt */
+
+ mtx_lock_spin(&xlr_pic_lock);
+ xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff));
+ xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff);
+ xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
+ xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1<<31)|(0<<30)|(1<<6)|(PIC_TIMER_7_IRQ));
+ pic_update_control(1<<(8+7));
+
+ xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
+ xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0x0) & 0xffffffff);
+ xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
+ xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1<<31)|(0<<30)|(1<<6)|(PIC_TIMER_6_IRQ));
+ pic_update_control(1<<(8+6));
+ mtx_unlock_spin(&xlr_pic_lock);
+ } else {
+ /* Setup count-compare interrupt for vcpu[1-31] */
+ mips_wr_compare((xlr_boot1_info.cpu_frequency)/hz);
+ }
+}
+
+
+
+unsigned __attribute__((no_instrument_function))
+platform_get_timecount(struct timecounter *tc)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
+}
Added: projects/mips/sys/mips/rmi/clock.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/clock.h Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,40 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _RMI_CLOCK_H_
+#define _RMI_CLOCK_H_
+
+#define XLR_PIC_HZ 66000000U
+#define XLR_CPU_HZ (xlr_boot1_info.cpu_frequency)
+
+void count_compare_clockhandler(struct trapframe *);
+void pic_hardclockhandler(struct trapframe *);
+void pic_timecounthandler(struct trapframe *);
+
+#endif /* _RMI_CLOCK_H_ */
Added: projects/mips/sys/mips/rmi/debug.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/debug.h Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,103 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _RMI_DEBUG_H_
+#define _RMI_DEBUG_H_
+
+#include <machine/atomic.h>
+
+enum {
+ //cacheline 0
+ MSGRNG_INT,
+ MSGRNG_PIC_INT,
+ MSGRNG_MSG,
+ MSGRNG_EXIT_STATUS,
+ MSGRNG_MSG_CYCLES,
+ //cacheline 1
+ NETIF_TX = 8,
+ NETIF_RX,
+ NETIF_TX_COMPLETE,
+ NETIF_TX_COMPLETE_TX,
+ NETIF_RX_CYCLES,
+ NETIF_TX_COMPLETE_CYCLES,
+ NETIF_TX_CYCLES,
+ NETIF_TIMER_START_Q,
+ //NETIF_REG_FRIN,
+ //NETIF_INT_REG,
+ //cacheline 2
+ REPLENISH_ENTER = 16,
+ REPLENISH_ENTER_COUNT,
+ REPLENISH_CPU,
+ REPLENISH_FRIN,
+ REPLENISH_CYCLES,
+ NETIF_STACK_TX,
+ NETIF_START_Q,
+ NETIF_STOP_Q,
+ //cacheline 3
+ USER_MAC_START = 24,
+ USER_MAC_INT = 24,
+ USER_MAC_TX_COMPLETE,
+ USER_MAC_RX,
+ USER_MAC_POLL,
+ USER_MAC_TX,
+ USER_MAC_TX_FAIL,
+ USER_MAC_TX_COUNT,
+ USER_MAC_FRIN,
+ //cacheline 4
+ USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
+ USER_MAC_DO_PAGE_FAULT,
+ USER_MAC_UPDATE_TLB,
+ USER_MAC_UPDATE_BIGTLB,
+ USER_MAC_UPDATE_TLB_PFN0,
+ USER_MAC_UPDATE_TLB_PFN1,
+
+ XLR_MAX_COUNTERS = 40
+};
+extern int xlr_counters[MAXCPU][XLR_MAX_COUNTERS];
+extern __uint32_t msgrng_msg_cycles;
+
+#ifdef ENABLE_DEBUG
+#define xlr_inc_counter(x) atomic_add_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1)
+#define xlr_dec_counter(x) atomic_subtract_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1)
+#define xlr_set_counter(x, value) atomic_set_int(&xlr_counters[PCPU_GET(cpuid)][(x)], (value))
+#define xlr_get_counter(x) (&xlr_counters[0][(x)])
+
+#else /* default mode */
+
+#define xlr_inc_counter(x)
+#define xlr_dec_counter(x)
+#define xlr_set_counter(x, value)
+#define xlr_get_counter(x)
+
+#endif
+
+#define dbg_msg(fmt, args...) printf(fmt, ##args)
+#define dbg_panic(fmt, args...) panic(fmt, ##args)
+
+#endif
Added: projects/mips/sys/mips/rmi/interrupt.h
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/interrupt.h Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,43 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+#ifndef _RMI_INTERRUPT_H_
+#define _RMI_INTERRUPT_H_
+
+/* Defines for the IRQ numbers */
+
+#define IRQ_DUMMY_UART 2
+#define IRQ_IPI_SMP_FUNCTION 3
+#define IRQ_IPI_SMP_RESCHEDULE 4
+#define IRQ_REMOTE_DEBUG 5
+#define IRQ_MSGRING 6
+#define IRQ_TIMER 7
+
+#endif /* _RMI_INTERRUPT_H_ */
+
Added: projects/mips/sys/mips/rmi/iodi.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/iodi.c Thu Oct 15 21:14:42 2009 (r198160)
@@ -0,0 +1,272 @@
+/*-
+ * Copyright (c) 2003-2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of RMI Corporation, nor the names of its contributors,
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RMI_BSD */
+
+#define __RMAN_RESOURCE_VISIBLE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/reboot.h>
+#include <sys/types.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <sys/module.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+#include <machine/bus.h>
+#include <machine/intr_machdep.h>
+#include <mips/xlr/iomap.h>
+#include <mips/xlr/pic.h>
+#include <mips/xlr/board.h>
+#include <sys/rman.h>
+
+extern void iodi_activateirqs(void);
+
+extern bus_space_tag_t uart_bus_space_mem;
+
+static struct resource *iodi_alloc_resource(device_t, device_t, int, int *,
+ u_long, u_long, u_long, u_int);
+
+static int iodi_activate_resource(device_t, device_t, int, int,
+ struct resource *);
+static int iodi_setup_intr(device_t, device_t, struct resource *, int,
+ driver_intr_t *, void *, void **);
+
+struct iodi_softc *iodi_softc; /* There can be only one. */
+
+static void pic_usb_ack(void *arg)
+{
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ int irq = PIC_USB_IRQ ;
+
+ mtx_lock_spin(&xlr_pic_lock);
+ xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
+ mtx_unlock_spin(&xlr_pic_lock);
+}
+
+static int
+iodi_setup_intr(device_t dev, device_t child,
+ struct resource *ires, int flags, driver_intr_t *intr, void *arg,
+ void **cookiep)
+{
+ int level;
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+ xlr_reg_t reg;
+
+ /* FIXME is this the right place to fiddle with PIC? */
+ if (strcmp(device_get_name(child),"uart") == 0) {
+ /* FIXME uart 1? */
+ mtx_lock_spin(&xlr_pic_lock);
+ level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
+ xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
+ xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level<<30)|(1<<6)|(PIC_UART_0_IRQ)));
+ mtx_unlock_spin(&xlr_pic_lock);
+
+ cpu_establish_intr("uart", PIC_UART_0_IRQ,
+ (driver_intr_t *)intr, (void *)arg, flags, cookiep,
+ NULL, NULL);
+
+ } else if (strcmp(device_get_name(child),"rge") == 0) {
+ mtx_lock_spin(&xlr_pic_lock);
+ reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + ires->r_flags - PIC_IRQ_BASE);
+ xlr_write_reg(mmio, PIC_IRT_1_BASE + ires->r_flags - PIC_IRQ_BASE, reg | (1<<6)|(1<<30)| (1<<31));
+ mtx_unlock_spin(&xlr_pic_lock);
+ cpu_establish_intr("rge", ires->r_flags,
+ (driver_intr_t *)intr, (void *)arg,
+ flags, cookiep, NULL, NULL);
+ } else if (strcmp(device_get_name(child),"ehci") == 0) {
+ mtx_lock_spin(&xlr_pic_lock);
+ reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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