svn commit: r198956 - projects/mips/sys/mips/rmi
Randall Stewart
rrs at FreeBSD.org
Thu Nov 5 18:14:27 UTC 2009
Author: rrs
Date: Thu Nov 5 18:14:25 2009
New Revision: 198956
URL: http://svn.freebsd.org/changeset/base/198956
Log:
ok we now get so that the uart init's and we can print. We
cannot set baud rate as they did in 6.4, this hoses things and
we loose our 38400 default term.
We now lock somewhere in tcinit.
Added:
projects/mips/sys/mips/rmi/bus_space_rmi.c
Modified:
projects/mips/sys/mips/rmi/clock.c
projects/mips/sys/mips/rmi/clock.h
projects/mips/sys/mips/rmi/files.xlr
projects/mips/sys/mips/rmi/iodi.c
projects/mips/sys/mips/rmi/iomap.h
projects/mips/sys/mips/rmi/msgring.h
projects/mips/sys/mips/rmi/on_chip.c
projects/mips/sys/mips/rmi/pcibus.c
projects/mips/sys/mips/rmi/pic.h
projects/mips/sys/mips/rmi/uart_bus_xlr_iodi.c
projects/mips/sys/mips/rmi/uart_cpu_mips_xlr.c
projects/mips/sys/mips/rmi/xlr_machdep.c
Added: projects/mips/sys/mips/rmi/bus_space_rmi.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/mips/sys/mips/rmi/bus_space_rmi.c Thu Nov 5 18:14:25 2009 (r198956)
@@ -0,0 +1,795 @@
+/*-
+ * Copyright (c) 2009 RMI Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/ktr.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_kern.h>
+#include <vm/vm_extern.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+void xlr_putc(char);
+void xlr_print_int(uint32_t);
+
+static int rmi_bus_space_map(void *t, bus_addr_t addr,
+ bus_size_t size, int flags,
+ bus_space_handle_t *bshp);
+
+
+static void rmi_bus_space_unmap(void *t, bus_space_handle_t bsh,
+ bus_size_t size);
+
+static int rmi_bus_space_subregion(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size,
+ bus_space_handle_t *nbshp);
+
+static u_int8_t rmi_bus_space_read_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t rmi_bus_space_read_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t rmi_bus_space_read_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset);
+
+static void rmi_bus_space_read_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_region_1(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+static void rmi_bus_space_write_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value);
+
+static void rmi_bus_space_write_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void rmi_bus_space_write_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void rmi_bus_space_write_multi_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t *addr,
+ size_t count);
+static void rmi_bus_space_write_multi_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static void rmi_bus_space_write_multi_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+static void rmi_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static void rmi_bus_space_write_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+
+static void rmi_bus_space_set_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value,
+ size_t count);
+static void rmi_bus_space_set_region_4(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value,
+ size_t count);
+
+static void rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags);
+
+
+static void rmi_bus_space_copy_region_2(void *t,
+ bus_space_handle_t bsh1,
+ bus_size_t off1,
+ bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count);
+
+u_int8_t rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int16_t rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+
+static u_int32_t rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset);
+static void rmi_bus_space_read_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr,
+ size_t count);
+
+static void rmi_bus_space_read_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr,
+ size_t count);
+
+void rmi_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t value);
+static void rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value);
+
+static void rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value);
+
+static void rmi_bus_space_write_multi_stream_1(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int8_t *addr,
+ size_t count);
+static void rmi_bus_space_write_multi_stream_2(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count);
+
+static void rmi_bus_space_write_multi_stream_4(void *t,
+ bus_space_handle_t handle,
+ bus_size_t offset,
+ const u_int32_t *addr,
+ size_t count);
+
+
+static struct bus_space local_rmi_bus_space = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ rmi_bus_space_map,
+ rmi_bus_space_unmap,
+ rmi_bus_space_subregion,
+
+ /* allocation/deallocation */
+ NULL,
+ NULL,
+
+ /* barrier */
+ rmi_bus_space_barrier,
+
+ /* read (single) */
+ rmi_bus_space_read_1,
+ rmi_bus_space_read_2,
+ rmi_bus_space_read_4,
+ NULL,
+
+ /* read multiple */
+ rmi_bus_space_read_multi_1,
+ rmi_bus_space_read_multi_2,
+ rmi_bus_space_read_multi_4,
+ NULL,
+
+ /* read region */
+ rmi_bus_space_read_region_1,
+ rmi_bus_space_read_region_2,
+ rmi_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) */
+ rmi_bus_space_write_1,
+ rmi_bus_space_write_2,
+ rmi_bus_space_write_4,
+ NULL,
+
+ /* write multiple */
+ rmi_bus_space_write_multi_1,
+ rmi_bus_space_write_multi_2,
+ rmi_bus_space_write_multi_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ rmi_bus_space_write_region_2,
+ rmi_bus_space_write_region_4,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ rmi_bus_space_set_region_2,
+ rmi_bus_space_set_region_4,
+ NULL,
+
+ /* copy */
+ NULL,
+ rmi_bus_space_copy_region_2,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ rmi_bus_space_read_stream_1,
+ rmi_bus_space_read_stream_2,
+ rmi_bus_space_read_stream_4,
+ NULL,
+
+ /* read multiple stream */
+ rmi_bus_space_read_multi_stream_1,
+ rmi_bus_space_read_multi_stream_2,
+ rmi_bus_space_read_multi_stream_4,
+ NULL,
+
+ /* read region stream */
+ rmi_bus_space_read_region_1,
+ rmi_bus_space_read_region_2,
+ rmi_bus_space_read_region_4,
+ NULL,
+
+ /* write (single) stream */
+ rmi_bus_space_write_stream_1,
+ rmi_bus_space_write_stream_2,
+ rmi_bus_space_write_stream_4,
+ NULL,
+
+ /* write multiple stream */
+ rmi_bus_space_write_multi_stream_1,
+ rmi_bus_space_write_multi_stream_2,
+ rmi_bus_space_write_multi_stream_4,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ rmi_bus_space_write_region_2,
+ rmi_bus_space_write_region_4,
+ NULL,
+};
+
+/* generic bus_space tag */
+bus_space_tag_t rmi_bus_space = &local_rmi_bus_space;
+
+#define MIPS_BUS_SPACE_IO 0 /* space is i/o space */
+#define MIPS_BUS_SPACE_MEM 1 /* space is mem space */
+#define MIPS_BUS_SPACE_PCI 10 /* avoid conflict with other spaces */
+
+#define BUS_SPACE_UNRESTRICTED (~0)
+
+#define SWAP32(x)\
+ (((x) & 0xff000000) >> 24) | \
+ (((x) & 0x000000ff) << 24) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x00ff0000) >> 8)
+
+#define SWAP16(x)\
+ (((x) & 0xff00) >> 8) | \
+ (((x) & 0x00ff) << 8)
+
+/*
+ * Map a region of device bus space into CPU virtual address space.
+ */
+
+
+static int
+rmi_bus_space_map(void *t __unused, bus_addr_t addr,
+ bus_size_t size __unused, int flags __unused,
+ bus_space_handle_t *bshp)
+{
+
+ *bshp = addr;
+ return (0);
+}
+
+/*
+ * Unmap a region of device bus space.
+ */
+static void
+rmi_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
+ bus_size_t size __unused)
+{
+}
+
+/*
+ * Get a new handle for a subregion of an already-mapped area of bus space.
+ */
+
+static int
+rmi_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
+ bus_size_t offset, bus_size_t size __unused,
+ bus_space_handle_t *nbshp)
+{
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+/*
+ * Read a 1, 2, 4, or 8 byte quantity from bus space
+ * described by tag/handle/offset.
+ */
+
+static u_int8_t
+rmi_bus_space_read_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ if ((int)tag == MIPS_BUS_SPACE_PCI)
+ return (u_int8_t)(*(volatile u_int8_t *)(handle + offset));
+ else
+ return (u_int8_t)(*(volatile u_int32_t *)(handle + offset));
+}
+
+static u_int16_t
+rmi_bus_space_read_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ if ((int)tag == MIPS_BUS_SPACE_PCI)
+ return SWAP16((u_int16_t)(*(volatile u_int16_t *)(handle + offset)));
+ else
+ return *(volatile u_int16_t *)(handle + offset);
+}
+
+static u_int32_t
+rmi_bus_space_read_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ if ((int)tag == MIPS_BUS_SPACE_PCI)
+ return SWAP32((*(volatile u_int32_t *)(handle + offset)));
+ else
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+static void
+rmi_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ *addr = (*(volatile u_int8_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ *addr = *(volatile u_int16_t *)(handle + offset);
+ *addr = SWAP16(*addr);
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ *addr = *(volatile u_int32_t *)(handle + offset);
+ *addr = SWAP32(*addr);
+ addr++;
+ }
+}
+
+/*
+ * Write the 1, 2, 4, or 8 byte value `value' to bus space
+ * described by tag/handle/offset.
+ */
+
+
+static void
+rmi_bus_space_write_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ mips_sync();
+ if ((int)tag == MIPS_BUS_SPACE_PCI)
+ *(volatile u_int8_t *)(handle + offset) = value;
+ else
+ *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value;
+}
+
+static void
+rmi_bus_space_write_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ mips_sync();
+ if ((int)tag == MIPS_BUS_SPACE_PCI) {
+ *(volatile u_int16_t *)(handle + offset) = SWAP16(value);
+ } else
+ *(volatile u_int16_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_bus_space_write_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ mips_sync();
+ if ((int)tag == MIPS_BUS_SPACE_PCI) {
+ *(volatile u_int32_t *)(handle + offset) = SWAP32(value);
+ } else
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte quantities from the buffer
+ * provided to bus space described by tag/handle/offset.
+ */
+
+
+static void
+rmi_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t *addr, size_t count)
+{
+ mips_sync();
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ (*(volatile u_int8_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t *addr, size_t count)
+{
+ mips_sync();
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ (*(volatile u_int16_t *)(handle + offset)) = SWAP16(*addr);
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t *addr, size_t count)
+{
+ mips_sync();
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ (*(volatile u_int32_t *)(handle + offset)) = SWAP32(*addr);
+ addr++;
+ }
+}
+
+/*
+ * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
+ * by tag/handle starting at `offset'.
+ */
+
+static void
+rmi_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 2)
+ (*(volatile u_int16_t *)(addr)) = value;
+}
+
+static void
+rmi_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t value, size_t count)
+{
+ bus_addr_t addr = bsh + offset;
+
+ for (; count != 0; count--, addr += 4)
+ (*(volatile u_int32_t *)(addr)) = value;
+}
+
+
+/*
+ * Copy `count' 1, 2, 4, or 8 byte values from bus space starting
+ * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
+ */
+static void
+rmi_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
+ bus_size_t off1, bus_space_handle_t bsh2,
+ bus_size_t off2, size_t count)
+{
+ printf("bus_space_copy_region_2 - unimplemented\n");
+}
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle/offset and copy into buffer provided.
+ */
+
+u_int8_t
+rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+
+ return *((volatile u_int8_t *)(handle + offset));
+}
+
+
+static u_int16_t
+rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return *(volatile u_int16_t *)(handle + offset);
+}
+
+
+static u_int32_t
+rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset)
+{
+ return (*(volatile u_int32_t *)(handle + offset));
+}
+
+
+static void
+rmi_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ *addr = (*(volatile u_int8_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ *addr = (*(volatile u_int16_t *)(handle + offset));
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ *addr = (*(volatile u_int32_t *)(handle + offset));
+ addr++;
+ }
+}
+
+
+
+/*
+ * Read `count' 1, 2, 4, or 8 byte quantities from bus space
+ * described by tag/handle and starting at `offset' and copy into
+ * buffer provided.
+ */
+void
+rmi_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int8_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int8_t *)(baddr));
+ baddr += 1;
+ }
+}
+
+void
+rmi_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int16_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int16_t *)(baddr));
+ baddr += 2;
+ }
+}
+
+void
+rmi_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, u_int32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ *addr++ = (*(volatile u_int32_t *)(baddr));
+ baddr += 4;
+ }
+}
+
+
+void
+rmi_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int8_t value)
+{
+ mips_sync();
+ *(volatile u_int8_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int16_t value)
+{
+ mips_sync();
+ *(volatile u_int16_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
+ bus_size_t offset, u_int32_t value)
+{
+ mips_sync();
+ *(volatile u_int32_t *)(handle + offset) = value;
+}
+
+
+static void
+rmi_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int8_t *addr, size_t count)
+{
+ mips_sync();
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ (*(volatile u_int8_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int16_t *addr, size_t count)
+{
+ mips_sync();
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ (*(volatile u_int16_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+static void
+rmi_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
+ bus_size_t offset, const u_int32_t *addr, size_t count)
+{
+ mips_sync();
+ if ((int)tag != MIPS_BUS_SPACE_PCI)
+ return;
+ while (count--) {
+ (*(volatile u_int32_t *)(handle + offset)) = *addr;
+ addr++;
+ }
+}
+
+void
+rmi_bus_space_write_region_2(void *t,
+ bus_space_handle_t bsh,
+ bus_size_t offset,
+ const u_int16_t *addr,
+ size_t count)
+{
+ bus_addr_t baddr = (bus_addr_t)bsh + offset;
+ while (count--) {
+ (*(volatile u_int16_t *)(baddr)) = *addr;
+ addr++;
+ baddr += 2;
+ }
+}
+
+void
+rmi_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
+ bus_size_t offset, const u_int32_t *addr, size_t count)
+{
+ bus_addr_t baddr = bsh + offset;
+
+ while (count--) {
+ (*(volatile u_int32_t *)(baddr)) = *addr;
+ addr++;
+ baddr += 4;
+ }
+}
+
+static void
+rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
+ bus_size_t offset __unused, bus_size_t len __unused, int flags)
+{
+
+}
Modified: projects/mips/sys/mips/rmi/clock.c
==============================================================================
--- projects/mips/sys/mips/rmi/clock.c Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/clock.c Thu Nov 5 18:14:25 2009 (r198956)
@@ -163,6 +163,24 @@ pic_timecounthandler(struct trapframe *t
}
void
+rmi_early_counter_init()
+{
+ int cpu = PCPU_GET(cpuid);
+ xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
+
+ /* We do this to get the PIC time counter running right
+ * after system start. Otherwise the DELAY() function will
+ * not be able to work since it won't have a TC to read.
+ */
+ xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
+ xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
+ xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
+ xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
+ pic_update_control(1 << (8 + 6));
+}
+
+
+void
platform_initclocks(void)
{
int cpu = PCPU_GET(cpuid);
@@ -204,7 +222,8 @@ platform_initclocks(void)
/* Setup PIC Interrupt */
- mtx_lock_spin(&xlr_pic_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7 */
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff); /* 0x110 + 7 */
/* 0x40 + 8 */
@@ -221,7 +240,8 @@ platform_initclocks(void)
xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
pic_update_control(1 << (8 + 6));
- mtx_unlock_spin(&xlr_pic_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_unlock_spin(&xlr_pic_lock);
} else {
/* Setup count-compare interrupt for vcpu[1-31] */
mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
Modified: projects/mips/sys/mips/rmi/clock.h
==============================================================================
--- projects/mips/sys/mips/rmi/clock.h Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/clock.h Thu Nov 5 18:14:25 2009 (r198956)
@@ -36,5 +36,5 @@
void count_compare_clockhandler(struct trapframe *);
void pic_hardclockhandler(struct trapframe *);
int pic_timecounthandler(struct trapframe *);
-
+void rmi_early_counter_init(void);
#endif /* _RMI_CLOCK_H_ */
Modified: projects/mips/sys/mips/rmi/files.xlr
==============================================================================
--- projects/mips/sys/mips/rmi/files.xlr Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/files.xlr Thu Nov 5 18:14:25 2009 (r198956)
@@ -18,6 +18,7 @@ mips/rmi/pcibus.c optional pci
mips/rmi/xlr_pci.c optional pci
#mips/rmi/xls_ehci.c optional usb ehci
dev/rmi/xlr/rge.c optional rge
+mips/rmi/bus_space_rmi.c standard
dev/iicbus/xlr_rtc.c optional xlr_rtc
dev/iicbus/xlr_temperature.c optional xlr_temperature
dev/iicbus/xlr_eeprom.c optional xlr_eeprom
Modified: projects/mips/sys/mips/rmi/iodi.c
==============================================================================
--- projects/mips/sys/mips/rmi/iodi.c Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/iodi.c Thu Nov 5 18:14:25 2009 (r198956)
@@ -99,6 +99,7 @@ static void pic_usb_ack(void *arg)
}
*/
+
static int
iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t * filt, driver_intr_t * intr, void *arg,
@@ -111,11 +112,13 @@ iodi_setup_intr(device_t dev, device_t c
/* FIXME is this the right place to fiddle with PIC? */
if (strcmp(device_get_name(child), "uart") == 0) {
/* FIXME uart 1? */
- mtx_lock_spin(&xlr_pic_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level << 30) | (1 << 6) | (PIC_UART_0_IRQ)));
- mtx_unlock_spin(&xlr_pic_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("uart", NULL,
(driver_intr_t *) intr, (void *)arg, PIC_UART_0_IRQ, flags, cookiep);
@@ -123,16 +126,20 @@ iodi_setup_intr(device_t dev, device_t c
int irq;
irq = rman_get_rid(ires);
- mtx_lock_spin(&xlr_pic_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
- mtx_unlock_spin(&xlr_pic_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("rge", NULL, (driver_intr_t *) intr, (void *)arg, irq, flags, cookiep);
} else if (strcmp(device_get_name(child), "ehci") == 0) {
+ if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
+ if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("ehci", NULL, (driver_intr_t *) intr, (void *)arg, PIC_USB_IRQ, flags, cookiep);
}
Modified: projects/mips/sys/mips/rmi/iomap.h
==============================================================================
--- projects/mips/sys/mips/rmi/iomap.h Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/iomap.h Thu Nov 5 18:14:25 2009 (r198956)
@@ -31,7 +31,7 @@
#define _RMI_IOMAP_H_
#include <machine/endian.h>
-
+#define XLR_DEVICE_REGISTER_BASE 0x1EF00000
#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL
#define XLR_IO_SIZE 0x1000
@@ -65,6 +65,9 @@
#define XLR_IO_UART_0_OFFSET 0x14000
#define XLR_IO_UART_1_OFFSET 0x15000
+#define XLR_UART0ADDR (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE)
+
+
#define XLR_IO_I2C_0_OFFSET 0x16000
#define XLR_IO_I2C_1_OFFSET 0x17000
Modified: projects/mips/sys/mips/rmi/msgring.h
==============================================================================
--- projects/mips/sys/mips/rmi/msgring.h Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/msgring.h Thu Nov 5 18:14:25 2009 (r198956)
@@ -469,14 +469,15 @@ extern struct stn_cc xls_cc_table_pcie;
extern struct stn_cc xls_cc_table_dma;
extern struct stn_cc xls_cc_table_sec;
+
#define msgrng_access_save(lock, mflags) do { \
- mtx_lock_spin(lock); \
+ if (rmi_spin_mutex_safe) mtx_lock_spin(lock); \
msgrng_flags_save(mflags); \
}while(0)
#define msgrng_access_restore(lock, mflags) do { \
msgrng_flags_restore(mflags); \
- mtx_unlock_spin(lock); \
+ if (rmi_spin_mutex_safe) mtx_unlock_spin(lock); \
}while(0)
#define msgrng_access_enable(mflags) do { \
Modified: projects/mips/sys/mips/rmi/on_chip.c
==============================================================================
--- projects/mips/sys/mips/rmi/on_chip.c Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/on_chip.c Thu Nov 5 18:14:25 2009 (r198956)
@@ -262,10 +262,12 @@ register_msgring_handler(int major,
//dbg_msg("major=%d, action=%p, dev_id=%p\n", major, action, dev_id);
- mtx_lock_spin(&msgrng_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_lock_spin(&msgrng_lock);
tx_stn_handlers[major].action = action;
tx_stn_handlers[major].dev_id = dev_id;
- mtx_unlock_spin(&msgrng_lock);
+ if (rmi_spin_mutex_safe)
+ mtx_unlock_spin(&msgrng_lock);
if (xlr_test_and_set(&msgring_int_enabled)) {
platform_prep_smp_launch();
@@ -301,6 +303,7 @@ pic_init(void)
*/
xlr_write_reg(mmio, PIC_IRT_1_BASE + i, (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
}
+ dbg_msg("PIC init now done\n");
}
void
Modified: projects/mips/sys/mips/rmi/pcibus.c
==============================================================================
--- projects/mips/sys/mips/rmi/pcibus.c Thu Nov 5 17:22:12 2009 (r198955)
+++ projects/mips/sys/mips/rmi/pcibus.c Thu Nov 5 18:14:25 2009 (r198956)
@@ -148,7 +148,6 @@ static void pic_pcie_ack(void *arg)
*/
-
int
mips_platform_pci_setup_intr(device_t dev, device_t child,
struct resource *irq, int flags,
@@ -174,21 +173,22 @@ mips_platform_pci_setup_intr(device_t de
return 0;
if (xlr_board_info.is_xls == 0) {
- mtx_lock_spin(&xlr_pic_lock);
+
+ if (rmi_spin_mutex_safe) mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_PCIX_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_PCIX, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level << 30) |
(1 << 6) | (PIC_PCIX_IRQ)));
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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