svn commit: r189190 - in projects/jbuild/sys/arm: arm at91 conf
include mv mv/discovery mv/kirkwood mv/orion sa11x0
xscale/i8134x xscale/ixp425
John Birrell
jb at FreeBSD.org
Sat Feb 28 09:59:42 PST 2009
Author: jb
Date: Sat Feb 28 17:59:41 2009
New Revision: 189190
URL: http://svn.freebsd.org/changeset/base/189190
Log:
MFC
Added:
projects/jbuild/sys/arm/arm/cpufunc_asm_sheeva.S
- copied unchanged from r189173, head/sys/arm/arm/cpufunc_asm_sheeva.S
Deleted:
projects/jbuild/sys/arm/arm/cpufunc_asm_feroceon.S
Modified:
projects/jbuild/sys/arm/arm/busdma_machdep.c
projects/jbuild/sys/arm/arm/cpufunc.c
projects/jbuild/sys/arm/arm/dump_machdep.c
projects/jbuild/sys/arm/arm/elf_trampoline.c
projects/jbuild/sys/arm/arm/genassym.c
projects/jbuild/sys/arm/arm/machdep.c
projects/jbuild/sys/arm/arm/pmap.c
projects/jbuild/sys/arm/arm/swtch.S
projects/jbuild/sys/arm/arm/vm_machdep.c
projects/jbuild/sys/arm/at91/at91.c
projects/jbuild/sys/arm/at91/at91_mci.c
projects/jbuild/sys/arm/at91/at91_twi.c
projects/jbuild/sys/arm/at91/at91_twireg.h
projects/jbuild/sys/arm/at91/at91var.h
projects/jbuild/sys/arm/at91/files.at91
projects/jbuild/sys/arm/at91/uart_bus_at91usart.c
projects/jbuild/sys/arm/at91/uart_cpu_at91rm9200usart.c
projects/jbuild/sys/arm/at91/uart_dev_at91usart.c
projects/jbuild/sys/arm/conf/AVILA
projects/jbuild/sys/arm/conf/AVILA.hints
projects/jbuild/sys/arm/conf/BWCT
projects/jbuild/sys/arm/conf/CAMBRIA
projects/jbuild/sys/arm/conf/HL200
projects/jbuild/sys/arm/conf/KB920X
projects/jbuild/sys/arm/conf/NSLU
projects/jbuild/sys/arm/include/atomic.h
projects/jbuild/sys/arm/include/cpufunc.h
projects/jbuild/sys/arm/include/proc.h
projects/jbuild/sys/arm/include/sysarch.h
projects/jbuild/sys/arm/include/vmparam.h
projects/jbuild/sys/arm/mv/common.c
projects/jbuild/sys/arm/mv/discovery/db78xxx.c
projects/jbuild/sys/arm/mv/discovery/discovery.c
projects/jbuild/sys/arm/mv/files.mv
projects/jbuild/sys/arm/mv/gpio.c
projects/jbuild/sys/arm/mv/kirkwood/db88f6xxx.c
projects/jbuild/sys/arm/mv/kirkwood/kirkwood.c
projects/jbuild/sys/arm/mv/mv_machdep.c
projects/jbuild/sys/arm/mv/mv_pci.c
projects/jbuild/sys/arm/mv/mvreg.h
projects/jbuild/sys/arm/mv/mvvar.h
projects/jbuild/sys/arm/mv/obio.c
projects/jbuild/sys/arm/mv/orion/db88f5xxx.c
projects/jbuild/sys/arm/mv/orion/orion.c
projects/jbuild/sys/arm/sa11x0/assabet_machdep.c
projects/jbuild/sys/arm/xscale/i8134x/i81342_mcu.c
projects/jbuild/sys/arm/xscale/ixp425/avila_machdep.c
projects/jbuild/sys/arm/xscale/ixp425/files.ixp425
projects/jbuild/sys/arm/xscale/ixp425/ixp425.c
projects/jbuild/sys/arm/xscale/ixp425/ixp425reg.h
Modified: projects/jbuild/sys/arm/arm/busdma_machdep.c
==============================================================================
--- projects/jbuild/sys/arm/arm/busdma_machdep.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/busdma_machdep.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -112,6 +112,7 @@ struct bounce_zone {
int active_bpages;
int total_bounced;
int total_deferred;
+ int map_count;
bus_size_t alignment;
bus_size_t boundary;
bus_addr_t lowaddr;
@@ -523,7 +524,7 @@ bus_dmamap_create(bus_dma_tag_t dmat, in
*/
maxpages = MAX_BPAGES;
if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0
- || (dmat->map_count > 0 && bz->total_bpages < maxpages)) {
+ || (bz->map_count > 0 && bz->total_bpages < maxpages)) {
int pages;
pages = MAX(atop(dmat->maxsize), 1);
@@ -539,6 +540,7 @@ bus_dmamap_create(bus_dma_tag_t dmat, in
error = 0;
}
}
+ bz->map_count++;
}
CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d",
__func__, dmat, dmat->flags, error);
@@ -560,6 +562,8 @@ bus_dmamap_destroy(bus_dma_tag_t dmat, b
__func__, dmat, EBUSY);
return (EBUSY);
}
+ if (dmat->bounce_zone)
+ dmat->bounce_zone->map_count--;
dmat->map_count--;
CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat);
return (0);
@@ -1144,6 +1148,7 @@ _bus_dmamap_sync_bp(bus_dma_tag_t dmat,
cpu_l2cache_wb_range(bpage->vaddr,
bpage->datacount);
}
+ dmat->bounce_zone->total_bounced++;
}
if (op & BUS_DMASYNC_POSTREAD) {
if (bpage->vaddr_nocache == 0) {
@@ -1155,6 +1160,7 @@ _bus_dmamap_sync_bp(bus_dma_tag_t dmat,
bcopy((void *)(bpage->vaddr_nocache != 0 ?
bpage->vaddr_nocache : bpage->vaddr),
(void *)bpage->datavaddr, bpage->datacount);
+ dmat->bounce_zone->total_bounced++;
}
}
}
@@ -1166,7 +1172,7 @@ _bus_dma_buf_is_in_bp(bus_dmamap_t map,
STAILQ_FOREACH(bpage, &map->bpages, links) {
if ((vm_offset_t)buf >= bpage->datavaddr &&
- (vm_offset_t)buf + len < bpage->datavaddr +
+ (vm_offset_t)buf + len <= bpage->datavaddr +
bpage->datacount)
return (1);
}
@@ -1275,6 +1281,7 @@ alloc_bounce_zone(bus_dma_tag_t dmat)
bz->lowaddr = dmat->lowaddr;
bz->alignment = dmat->alignment;
bz->boundary = dmat->boundary;
+ bz->map_count = 0;
snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount);
busdma_zonecount++;
snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr);
@@ -1415,6 +1422,13 @@ add_bounce_page(bus_dma_tag_t dmat, bus_
bz->active_bpages++;
mtx_unlock(&bounce_lock);
+ if (dmat->flags & BUS_DMA_KEEP_PG_OFFSET) {
+ /* page offset needs to be preserved */
+ bpage->vaddr &= ~PAGE_MASK;
+ bpage->busaddr &= ~PAGE_MASK;
+ bpage->vaddr |= vaddr & PAGE_MASK;
+ bpage->busaddr |= vaddr & PAGE_MASK;
+ }
bpage->datavaddr = vaddr;
bpage->datacount = size;
STAILQ_INSERT_TAIL(&(map->bpages), bpage, links);
Modified: projects/jbuild/sys/arm/arm/cpufunc.c
==============================================================================
--- projects/jbuild/sys/arm/arm/cpufunc.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/cpufunc.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -358,7 +358,7 @@ struct cpu_functions armv5_ec_cpufuncs =
};
-struct cpu_functions feroceon_cpufuncs = {
+struct cpu_functions sheeva_cpufuncs = {
/* CPU functions */
cpufunc_id, /* id */
@@ -368,7 +368,7 @@ struct cpu_functions feroceon_cpufuncs =
cpufunc_control, /* control */
cpufunc_domains, /* Domain */
- feroceon_setttb, /* Setttb */
+ sheeva_setttb, /* Setttb */
cpufunc_faultstatus, /* Faultstatus */
cpufunc_faultaddress, /* Faultaddress */
@@ -387,17 +387,17 @@ struct cpu_functions feroceon_cpufuncs =
armv5_ec_icache_sync_range, /* icache_sync_range */
armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */
- feroceon_dcache_wbinv_range, /* dcache_wbinv_range */
- feroceon_dcache_inv_range, /* dcache_inv_range */
- feroceon_dcache_wb_range, /* dcache_wb_range */
+ sheeva_dcache_wbinv_range, /* dcache_wbinv_range */
+ sheeva_dcache_inv_range, /* dcache_inv_range */
+ sheeva_dcache_wb_range, /* dcache_wb_range */
armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */
- feroceon_idcache_wbinv_range, /* idcache_wbinv_all */
+ sheeva_idcache_wbinv_range, /* idcache_wbinv_all */
- feroceon_l2cache_wbinv_all, /* l2cache_wbinv_all */
- feroceon_l2cache_wbinv_range, /* l2cache_wbinv_range */
- feroceon_l2cache_inv_range, /* l2cache_inv_range */
- feroceon_l2cache_wb_range, /* l2cache_wb_range */
+ sheeva_l2cache_wbinv_all, /* l2cache_wbinv_all */
+ sheeva_l2cache_wbinv_range, /* l2cache_wbinv_range */
+ sheeva_l2cache_inv_range, /* l2cache_inv_range */
+ sheeva_l2cache_wb_range, /* l2cache_wb_range */
/* Other functions */
@@ -1000,7 +1000,7 @@ set_cpufuncs()
cputype == CPU_ID_MV88FR571_VD ||
cputype == CPU_ID_MV88FR571_41) {
- cpufuncs = feroceon_cpufuncs;
+ cpufuncs = sheeva_cpufuncs;
/*
* Workaround for Marvell MV78100 CPU: Cache prefetch
* mechanism may affect the cache coherency validity,
@@ -1011,12 +1011,12 @@ set_cpufuncs()
*/
if (cputype == CPU_ID_MV88FR571_VD ||
cputype == CPU_ID_MV88FR571_41) {
- feroceon_control_ext(0xffffffff,
+ sheeva_control_ext(0xffffffff,
FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN |
FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN |
FC_L2_PREF_DIS);
} else {
- feroceon_control_ext(0xffffffff,
+ sheeva_control_ext(0xffffffff,
FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN |
FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN);
}
Copied: projects/jbuild/sys/arm/arm/cpufunc_asm_sheeva.S (from r189173, head/sys/arm/arm/cpufunc_asm_sheeva.S)
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ projects/jbuild/sys/arm/arm/cpufunc_asm_sheeva.S Sat Feb 28 17:59:41 2009 (r189190, copy of r189173, head/sys/arm/arm/cpufunc_asm_sheeva.S)
@@ -0,0 +1,386 @@
+/*-
+ * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
+ * All rights reserved.
+ *
+ * Developed by Semihalf.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of MARVELL nor the names of contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/asm.h>
+__FBSDID("$FreeBSD$");
+
+#include <machine/param.h>
+
+.Lsheeva_cache_line_size:
+ .word _C_LABEL(arm_pdcache_line_size)
+.Lsheeva_asm_page_mask:
+ .word _C_LABEL(PAGE_MASK)
+
+ENTRY(sheeva_setttb)
+ /* Disable irqs */
+ mrs r2, cpsr
+ orr r3, r2, #I32_bit | F32_bit
+ msr cpsr_c, r3
+
+ mov r1, #0
+ mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */
+1: mrc p15, 0, r15, c7, c14, 3 /* Test, clean and invalidate DCache */
+ bne 1b /* More to do? */
+
+ mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */
+ mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */
+
+ /* Reenable irqs */
+ msr cpsr_c, r2
+
+ mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
+
+ mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
+
+ mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ RET
+
+ENTRY(sheeva_dcache_wbinv_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
+ mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ add r0, r0, ip
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_idcache_wbinv_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
+ mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ /* Invalidate and clean icache line by line */
+ ldr r3, .Lsheeva_cache_line_size
+ ldr r3, [r3]
+2:
+ mcr p15, 0, r0, c7, c5, 1
+ add r0, r0, r3
+ cmp r2, r0
+ bhi 2b
+
+ add r0, r2, #1
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_dcache_inv_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */
+ mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ add r0, r0, ip
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_dcache_wb_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 5, r0, c15, c13, 0 /* Clean zone start address */
+ mcr p15, 5, r2, c15, c13, 1 /* Clean zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ add r0, r0, ip
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_l2cache_wbinv_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
+ mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
+ mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */
+ mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ add r0, r0, ip
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_l2cache_inv_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */
+ mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ add r0, r0, ip
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_l2cache_wb_range)
+ str lr, [sp, #-4]!
+ mrs lr, cpsr
+ /* Start with cache line aligned address */
+ ldr ip, .Lsheeva_cache_line_size
+ ldr ip, [ip]
+ sub ip, ip, #1
+ and r2, r0, ip
+ add r1, r1, r2
+ add r1, r1, ip
+ bics r1, r1, ip
+ bics r0, r0, ip
+
+ ldr ip, .Lsheeva_asm_page_mask
+ and r2, r0, ip
+ rsb r2, r2, #PAGE_SIZE
+ cmp r1, r2
+ movcc ip, r1
+ movcs ip, r2
+1:
+ add r3, r0, ip
+ sub r2, r3, #1
+ /* Disable irqs */
+ orr r3, lr, #I32_bit | F32_bit
+ msr cpsr_c, r3
+ mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
+ mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
+ /* Enable irqs */
+ msr cpsr_c, lr
+
+ add r0, r0, ip
+ sub r1, r1, ip
+ cmp r1, #PAGE_SIZE
+ movcc ip, r1
+ movcs ip, #PAGE_SIZE
+ cmp r1, #0
+ bne 1b
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ ldr lr, [sp], #4
+ RET
+
+ENTRY(sheeva_l2cache_wbinv_all)
+ mov r0, #0
+ mcr p15, 1, r0, c15, c9, 0 /* Clean L2 */
+ mcr p15, 1, r0, c15, c11, 0 /* Invalidate L2 */
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
+ RET
+
+ENTRY(sheeva_control_ext)
+ mrc p15, 1, r3, c15, c1, 0 /* Read the control register */
+ bic r2, r3, r0 /* Clear bits */
+ eor r2, r2, r1 /* XOR bits */
+
+ teq r2, r3 /* Only write if there is a change */
+ mcrne p15, 1, r2, c15, c1, 0 /* Write new control register */
+ mov r0, r3 /* Return old value */
+ RET
Modified: projects/jbuild/sys/arm/arm/dump_machdep.c
==============================================================================
--- projects/jbuild/sys/arm/arm/dump_machdep.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/dump_machdep.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -158,14 +158,12 @@ cb_dumpdata(struct md_pa *mdp, int seqnr
{
struct dumperinfo *di = (struct dumperinfo*)arg;
vm_paddr_t pa;
- vm_offset_t va;
uint32_t pgs;
size_t counter, sz, chunk;
int c, error;
error = 0; /* catch case in which chunk size is 0 */
counter = 0;
- va = 0;
pgs = mdp->md_size / PAGE_SIZE;
pa = mdp->md_start;
Modified: projects/jbuild/sys/arm/arm/elf_trampoline.c
==============================================================================
--- projects/jbuild/sys/arm/arm/elf_trampoline.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/elf_trampoline.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -74,7 +74,7 @@ void __startC(void);
#ifdef CPU_XSCALE_81342
#define cpu_l2cache_wbinv_all xscalec3_l2cache_purge
#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
-#define cpu_l2cache_wbinv_all feroceon_l2cache_wbinv_all
+#define cpu_l2cache_wbinv_all sheeva_l2cache_wbinv_all
#else
#define cpu_l2cache_wbinv_all()
#endif
@@ -404,11 +404,11 @@ load_kernel(unsigned int kstart, unsigne
int symtabindex = -1;
int symstrindex = -1;
vm_offset_t lastaddr = 0;
- Elf_Addr ssym = 0, esym = 0;
+ Elf_Addr ssym = 0;
Elf_Dyn *dp;
eh = (Elf32_Ehdr *)kstart;
- ssym = esym = 0;
+ ssym = 0;
entry_point = (void*)eh->e_entry;
memcpy(phdr, (void *)(kstart + eh->e_phoff ),
eh->e_phnum * sizeof(phdr[0]));
Modified: projects/jbuild/sys/arm/arm/genassym.c
==============================================================================
--- projects/jbuild/sys/arm/arm/genassym.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/genassym.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -96,6 +96,8 @@ ASSYM(TD_FRAME, offsetof(struct thread,
ASSYM(TD_MD, offsetof(struct thread, td_md));
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
ASSYM(MD_TP, offsetof(struct mdthread, md_tp));
+ASSYM(MD_RAS_START, offsetof(struct mdthread, md_ras_start));
+ASSYM(MD_RAS_END, offsetof(struct mdthread, md_ras_end));
ASSYM(TF_R0, offsetof(struct trapframe, tf_r0));
ASSYM(TF_R1, offsetof(struct trapframe, tf_r1));
Modified: projects/jbuild/sys/arm/arm/machdep.c
==============================================================================
--- projects/jbuild/sys/arm/arm/machdep.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/machdep.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -304,7 +304,6 @@ cpu_startup(void *dummy)
USPACE_SVC_STACK_TOP;
vector_page_setprot(VM_PROT_READ);
pmap_set_pcb_pagedir(pmap_kernel(), pcb);
- thread0.td_frame = (struct trapframe *)pcb->un_32.pcb32_sp - 1;
pmap_postinit();
#ifdef ARM_CACHE_LOCK_ENABLE
pmap_kenter_user(ARM_TP_ADDRESS, ARM_TP_ADDRESS);
Modified: projects/jbuild/sys/arm/arm/pmap.c
==============================================================================
--- projects/jbuild/sys/arm/arm/pmap.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/pmap.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -3102,7 +3102,7 @@ void
pmap_remove_all(vm_page_t m)
{
pv_entry_t pv;
- pt_entry_t *ptep, pte;
+ pt_entry_t *ptep;
struct l2_bucket *l2b;
boolean_t flush = FALSE;
pmap_t curpm;
@@ -3130,7 +3130,6 @@ pmap_remove_all(vm_page_t m)
l2b = pmap_get_l2_bucket(pv->pv_pmap, pv->pv_va);
KASSERT(l2b != NULL, ("No l2 bucket"));
ptep = &l2b->l2b_kva[l2pte_index(pv->pv_va)];
- pte = *ptep;
*ptep = 0;
PTE_SYNC_CURRENT(pv->pv_pmap, ptep);
pmap_free_l2_bucket(pv->pv_pmap, l2b, 1);
Modified: projects/jbuild/sys/arm/arm/swtch.S
==============================================================================
--- projects/jbuild/sys/arm/arm/swtch.S Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/swtch.S Sat Feb 28 17:59:41 2009 (r189190)
@@ -205,8 +205,12 @@ ENTRY(cpu_throw)
/* Set the new tp */
ldr r6, [r5, #(TD_MD + MD_TP)]
- ldr r5, =ARM_TP_ADDRESS
- strt r6, [r5]
+ ldr r4, =ARM_TP_ADDRESS
+ str r6, [r4]
+ ldr r6, [r5, #(TD_MD + MD_RAS_START)]
+ str r6, [r4, #4] /* ARM_RAS_START */
+ ldr r6, [r5, #(TD_MD + MD_RAS_END)]
+ str r6, [r4, #8] /* ARM_RAS_END */
/* Hook in a new pcb */
ldr r6, .Lcurpcb
@@ -265,12 +269,20 @@ ENTRY(cpu_switch)
*/
/* Store the old tp */
ldr r3, =ARM_TP_ADDRESS
- ldrt r9, [r3]
+ ldr r9, [r3]
str r9, [r0, #(TD_MD + MD_TP)]
+ ldr r9, [r3, #4]
+ str r9, [r0, #(TD_MD + MD_RAS_START)]
+ ldr r9, [r3, #8]
+ str r9, [r0, #(TD_MD + MD_RAS_END)]
/* Set the new tp */
ldr r9, [r1, #(TD_MD + MD_TP)]
- strt r9, [r3]
+ str r9, [r3]
+ ldr r9, [r1, #(TD_MD + MD_RAS_START)]
+ str r9, [r3, #4]
+ ldr r9, [r1, #(TD_MD + MD_RAS_END)]
+ str r9, [r3, #8]
/* Get the user structure for the new process in r9 */
ldr r9, [r1, #(TD_PCB)]
Modified: projects/jbuild/sys/arm/arm/vm_machdep.c
==============================================================================
--- projects/jbuild/sys/arm/arm/vm_machdep.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/arm/vm_machdep.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -108,14 +108,13 @@ void
cpu_fork(register struct thread *td1, register struct proc *p2,
struct thread *td2, int flags)
{
- struct pcb *pcb1, *pcb2;
+ struct pcb *pcb2;
struct trapframe *tf;
struct switchframe *sf;
struct mdproc *mdp2;
if ((flags & RFPROC) == 0)
return;
- pcb1 = td1->td_pcb;
pcb2 = (struct pcb *)(td2->td_kstack + td2->td_kstack_pages * PAGE_SIZE) - 1;
#ifdef __XSCALE__
#ifndef CPU_XSCALE_CORE3
Modified: projects/jbuild/sys/arm/at91/at91.c
==============================================================================
--- projects/jbuild/sys/arm/at91/at91.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/at91.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -50,6 +50,8 @@ static struct at91_softc *at91_softc;
static void at91_eoi(void *);
+uint32_t at91_master_clock = AT91C_MASTER_CLOCK;
+
static int
at91_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
Modified: projects/jbuild/sys/arm/at91/at91_mci.c
==============================================================================
--- projects/jbuild/sys/arm/at91/at91_mci.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/at91_mci.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -67,6 +67,9 @@ __FBSDID("$FreeBSD$");
struct at91_mci_softc {
void *intrhand; /* Interrupt handle */
device_t dev;
+ int sc_cap;
+#define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
+#define CAP_NEEDS_BOUNCE 2 /* broken hardware needing bounce */
int flags;
#define CMD_STARTED 1
#define STOP_STARTED 2
@@ -77,7 +80,6 @@ struct at91_mci_softc {
bus_dmamap_t map;
int mapped;
struct mmc_host host;
- int wire4;
int bus_busy;
struct mmc_request *req;
struct mmc_command *curcmd;
@@ -167,6 +169,7 @@ at91_mci_attach(device_t dev)
device_t child;
sc->dev = dev;
+ sc->sc_cap = CAP_NEEDS_BOUNCE;
err = at91_mci_activate(dev);
if (err)
goto out;
@@ -199,9 +202,12 @@ at91_mci_attach(device_t dev)
goto out;
}
sc->host.f_min = 375000;
- sc->host.f_max = 30000000;
+ sc->host.f_max = at91_master_clock / 2; /* Typically 30MHz */
sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
- sc->host.caps = MMC_CAP_4_BIT_DATA;
+ if (sc->sc_cap & CAP_HAS_4WIRE)
+ sc->host.caps = MMC_CAP_4_BIT_DATA;
+ else
+ sc->host.caps = 0;
child = device_add_child(dev, "mmc", 0);
device_set_ivars(dev, &sc->host);
err = bus_generic_attach(dev);
@@ -274,7 +280,6 @@ at91_mci_getaddr(void *arg, bus_dma_segm
static int
at91_mci_update_ios(device_t brdev, device_t reqdev)
{
- uint32_t at91_master_clock = AT91C_MASTER_CLOCK;
struct at91_mci_softc *sc;
struct mmc_host *host;
struct mmc_ios *ios;
@@ -294,11 +299,12 @@ at91_mci_update_ios(device_t brdev, devi
else
clkdiv = (at91_master_clock / ios->clock) / 2;
}
- if (ios->bus_width == bus_width_4 && sc->wire4)
+ if (ios->bus_width == bus_width_4)
WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
else
WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
+ /* Do we need a settle time here? */
/* XXX We need to turn the device on/off here with a GPIO pin */
return (0);
}
@@ -311,7 +317,6 @@ at91_mci_start_cmd(struct at91_mci_softc
int i;
struct mmc_data *data;
struct mmc_request *req;
- size_t block_size = 1 << 9; // Fixed, per mmc/sd spec for 2GB cards
void *vaddr;
bus_addr_t paddr;
@@ -353,19 +358,21 @@ at91_mci_start_cmd(struct at91_mci_softc
// Set block size and turn on PDC mode for dma xfer and disable
// PDC until we're ready.
mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN;
- WR4(sc, MCI_MR, mr | (block_size << 16) | MCI_MR_PDCMODE);
+ WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE);
WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
if (cmdr & MCI_CMDR_TRCMD_START) {
if (cmdr & MCI_CMDR_TRDIR)
vaddr = cmd->data->data;
else {
- if (data->len != BBSZ)
- panic("Write multiblock write support");
- vaddr = sc->bounce_buffer;
- src = (uint32_t *)cmd->data->data;
- dst = (uint32_t *)vaddr;
- for (i = 0; i < data->len / 4; i++)
- dst[i] = bswap32(src[i]);
+ if (sc->sc_cap & CAP_NEEDS_BOUNCE) {
+ vaddr = sc->bounce_buffer;
+ src = (uint32_t *)cmd->data->data;
+ dst = (uint32_t *)vaddr;
+ for (i = 0; i < data->len / 4; i++)
+ dst[i] = bswap32(src[i]);
+ }
+ else
+ vaddr = cmd->data->data;
}
data->xfer_len = 0;
if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len,
@@ -496,10 +503,12 @@ at91_mci_read_done(struct at91_mci_softc
bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->dmatag, sc->map);
sc->mapped--;
- walker = (uint32_t *)cmd->data->data;
- len = cmd->data->len / 4;
- for (i = 0; i < len; i++)
- walker[i] = bswap32(walker[i]);
+ if (sc->sc_cap & CAP_NEEDS_BOUNCE) {
+ walker = (uint32_t *)cmd->data->data;
+ len = cmd->data->len / 4;
+ for (i = 0; i < len; i++)
+ walker[i] = bswap32(walker[i]);
+ }
// Finish up the sequence...
WR4(sc, MCI_IDR, MCI_SR_ENDRX);
WR4(sc, MCI_IER, MCI_SR_RXBUFF);
@@ -643,6 +652,9 @@ at91_mci_read_ivar(device_t bus, device_
case MMCBR_IVAR_VDD:
*(int *)result = sc->host.ios.vdd;
break;
+ case MMCBR_IVAR_CAPS:
+ *(int *)result = sc->host.caps;
+ break;
case MMCBR_IVAR_MAX_DATA:
*(int *)result = 1;
break;
@@ -683,6 +695,7 @@ at91_mci_write_ivar(device_t bus, device
sc->host.ios.vdd = value;
break;
/* These are read-only */
+ case MMCBR_IVAR_CAPS:
case MMCBR_IVAR_HOST_OCR:
case MMCBR_IVAR_F_MIN:
case MMCBR_IVAR_F_MAX:
Modified: projects/jbuild/sys/arm/at91/at91_twi.c
==============================================================================
--- projects/jbuild/sys/arm/at91/at91_twi.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/at91_twi.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
#include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91_twireg.h>
+#include <arm/at91/at91var.h>
#include <dev/iicbus/iiconf.h>
#include <dev/iicbus/iicbus.h>
@@ -128,7 +129,7 @@ at91_twi_attach(device_t dev)
AT91_TWI_LOCK_DESTROY(sc);
goto out;
}
- sc->cwgr = TWI_CWGR_CKDIV(8 * AT91C_MASTER_CLOCK / TWI_FASTEST_CLOCK) |
+ sc->cwgr = TWI_CWGR_CKDIV(8 * at91_master_clock / TWI_FASTEST_CLOCK) |
TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
WR4(sc, TWI_CR, TWI_CR_SWRST);
Modified: projects/jbuild/sys/arm/at91/at91_twireg.h
==============================================================================
--- projects/jbuild/sys/arm/at91/at91_twireg.h Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/at91_twireg.h Sat Feb 28 17:59:41 2009 (r189190)
@@ -63,7 +63,7 @@
#define TWI_CWGR_CKDIV(x) ((x) << 16) /* Clock Divider */
#define TWI_CWGR_CHDIV(x) ((x) << 8) /* Clock High Divider */
#define TWI_CWGR_CLDIV(x) ((x) << 0) /* Clock Low Divider */
-#define TWI_CWGR_DIV(rate) ((AT91C_MASTER_CLOCK /(4*(rate))) - 2)
+#define TWI_CWGR_DIV(rate) ((at91_master_clock /(4*(rate))) - 2)
/* TWI_SR */
/* TWI_IER */
Modified: projects/jbuild/sys/arm/at91/at91var.h
==============================================================================
--- projects/jbuild/sys/arm/at91/at91var.h Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/at91var.h Sat Feb 28 17:59:41 2009 (r189190)
@@ -43,4 +43,6 @@ struct at91_ivar {
struct resource_list resources;
};
+extern uint32_t at91_master_clock;
+
#endif /* _AT91VAR_H_ */
Modified: projects/jbuild/sys/arm/at91/files.at91
==============================================================================
--- projects/jbuild/sys/arm/at91/files.at91 Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/files.at91 Sat Feb 28 17:59:41 2009 (r189190)
@@ -15,10 +15,10 @@ arm/at91/at91_tc.c optional at91_tc
arm/at91/at91_twi.c optional at91_twi
arm/at91/at91_udp.c optional at91_udp
arm/at91/if_ate.c optional ate
-arm/at91/ohci_atmelarm.c optional ohci
arm/at91/uart_bus_at91usart.c optional uart
arm/at91/uart_cpu_at91rm9200usart.c optional uart
arm/at91/uart_dev_at91usart.c optional uart
+dev/usb/controller/ohci_atmelarm.c optional ohci
#
# All the boards we support
#
Modified: projects/jbuild/sys/arm/at91/uart_bus_at91usart.c
==============================================================================
--- projects/jbuild/sys/arm/at91/uart_bus_at91usart.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/uart_bus_at91usart.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -38,13 +38,12 @@ __FBSDID("$FreeBSD$");
#include <sys/rman.h>
#include <machine/resource.h>
-#include <dev/pci/pcivar.h>
-
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include <arm/at91/at91rm92reg.h>
+#include <arm/at91/at91var.h>
#include "uart_if.h"
@@ -103,6 +102,8 @@ usart_at91rm92_probe(device_t dev)
break;
}
sc->sc_class = &at91_usart_class;
+ if (sc->sc_class->uc_rclk == 0)
+ sc->sc_class->uc_rclk = at91_master_clock;
return (uart_bus_probe(dev, 0, 0, 0, device_get_unit(dev)));
}
Modified: projects/jbuild/sys/arm/at91/uart_cpu_at91rm9200usart.c
==============================================================================
--- projects/jbuild/sys/arm/at91/uart_cpu_at91rm9200usart.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/uart_cpu_at91rm9200usart.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -35,12 +35,16 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
+#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include <arm/at91/at91rm92reg.h>
+#include <arm/at91/at91var.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
@@ -60,6 +64,8 @@ uart_cpu_getdev(int devtype, struct uart
struct uart_class *class;
class = &at91_usart_class;
+ if (class->uc_rclk == 0)
+ class->uc_rclk = at91_master_clock;
di->ops = uart_getops(class);
di->bas.chan = 0;
di->bas.bst = &at91_bs_tag;
Modified: projects/jbuild/sys/arm/at91/uart_dev_at91usart.c
==============================================================================
--- projects/jbuild/sys/arm/at91/uart_dev_at91usart.c Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/at91/uart_dev_at91usart.c Sat Feb 28 17:59:41 2009 (r189190)
@@ -45,10 +45,11 @@ __FBSDID("$FreeBSD$");
#include <arm/at91/at91rm92reg.h>
#include <arm/at91/at91_usartreg.h>
#include <arm/at91/at91_pdcreg.h>
+#include <arm/at91/at91var.h>
#include "uart_if.h"
-#define DEFAULT_RCLK AT91C_MASTER_CLOCK
+#define DEFAULT_RCLK at91_master_clock
#define USART_BUFFER_SIZE 128
/*
@@ -684,6 +685,5 @@ struct uart_class at91_usart_class = {
at91_usart_methods,
sizeof(struct at91_usart_softc),
.uc_ops = &at91_usart_ops,
- .uc_range = 8,
- .uc_rclk = DEFAULT_RCLK
+ .uc_range = 8
};
Modified: projects/jbuild/sys/arm/conf/AVILA
==============================================================================
--- projects/jbuild/sys/arm/conf/AVILA Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/conf/AVILA Sat Feb 28 17:59:41 2009 (r189190)
@@ -66,13 +66,15 @@ options BOOTP_COMPAT
device pci
device uart
+device ixpwdog # watchdog timer
+device cfi # flash support
+
# I2C Bus
device iicbus
device iicbb
device iic
device ixpiic # I2C bus glue
-device ixpwdog # watchdog timer
device ds1672 # DS1672 on I2C bus
device ad7418 # AD7418 on I2C bus
@@ -86,7 +88,7 @@ device npe # Network Processing Engine
device npe_fw
device firmware
device qmgr # Q Manager (required by npe)
-device miibus # NB: required by npe
+device mii # NB: required by npe
device ether
device bpf
@@ -131,7 +133,6 @@ device usb
#options USB_DEBUG
device ohci
device ehci
-device ugen
#device umass
#device scbus # SCSI bus (required for SCSI)
#device da # Direct Access (disks)
Modified: projects/jbuild/sys/arm/conf/AVILA.hints
==============================================================================
--- projects/jbuild/sys/arm/conf/AVILA.hints Sat Feb 28 17:59:29 2009 (r189189)
+++ projects/jbuild/sys/arm/conf/AVILA.hints Sat Feb 28 17:59:41 2009 (r189190)
@@ -29,6 +29,10 @@ hint.npe.1.mac="C"
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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