svn commit: r188808 - projects/mips/sys/mips/atheros

Oleksandr Tymoshenko gonzo at FreeBSD.org
Wed Feb 18 22:23:57 PST 2009


Author: gonzo
Date: Thu Feb 19 06:23:56 2009
New Revision: 188808
URL: http://svn.freebsd.org/changeset/base/188808

Log:
  - Driver for on-board AR71XX ethernet

Added:
  projects/mips/sys/mips/atheros/if_arge.c
  projects/mips/sys/mips/atheros/if_argevar.h

Added: projects/mips/sys/mips/atheros/if_arge.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ projects/mips/sys/mips/atheros/if_arge.c	Thu Feb 19 06:23:56 2009	(r188808)
@@ -0,0 +1,1657 @@
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * AR71XX gigabit ethernet driver
+ */
+#include <sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/socket.h>
+#include <sys/taskqueue.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+
+#include <net/bpf.h>
+
+#include <machine/bus.h>
+#include <machine/cache.h>
+#include <machine/resource.h>
+#include <vm/vm_param.h>
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <machine/pmap.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+
+MODULE_DEPEND(arge, ether, 1, 1, 1);
+MODULE_DEPEND(arge, miibus, 1, 1, 1);
+
+#include "miibus_if.h"
+
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/if_argevar.h>
+
+#undef ARGE_DEBUG
+#ifdef ARGE_DEBUG
+#define dprintf printf
+#else
+#define dprintf(x, arg...)
+#endif
+
+static int arge_attach(device_t);
+static int arge_detach(device_t);
+static int arge_fix_chain(struct mbuf **mp);
+static void arge_flush_ddr(struct arge_softc *);
+static int arge_ifmedia_upd(struct ifnet *);
+static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+static int arge_ioctl(struct ifnet *, u_long, caddr_t);
+static void arge_init(void *);
+static void arge_init_locked(struct arge_softc *);
+static void arge_link_task(void *, int);
+static int arge_miibus_readreg(device_t, int, int);
+static void arge_miibus_statchg(device_t);
+static int arge_miibus_writereg(device_t, int, int, int);
+static int arge_probe(device_t);
+static void arge_reset_dma(struct arge_softc *);
+static int arge_resume(device_t);
+static int arge_rx_ring_init(struct arge_softc *);
+static int arge_tx_ring_init(struct arge_softc *);
+static void arge_shutdown(device_t);
+static void arge_start(struct ifnet *);
+static void arge_start_locked(struct ifnet *);
+static void arge_stop(struct arge_softc *);
+static int arge_suspend(device_t);
+
+static void arge_rx_locked(struct arge_softc *);
+static void arge_tx_locked(struct arge_softc *);
+static void arge_intr(void *);
+static int arge_intr_filter(void *);
+static void arge_tx_intr(struct arge_softc *, uint32_t);
+static void arge_rx_intr(struct arge_softc *, uint32_t);
+static void arge_tick(void *);
+
+static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
+static int arge_dma_alloc(struct arge_softc *);
+static void arge_dma_free(struct arge_softc *);
+static int arge_newbuf(struct arge_softc *, int);
+static __inline void arge_fixup_rx(struct mbuf *);
+
+static device_method_t arge_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		arge_probe),
+	DEVMETHOD(device_attach,	arge_attach),
+	DEVMETHOD(device_detach,	arge_detach),
+	DEVMETHOD(device_suspend,	arge_suspend),
+	DEVMETHOD(device_resume,	arge_resume),
+	DEVMETHOD(device_shutdown,	arge_shutdown),
+
+	/* bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
+
+	/* MII interface */
+	DEVMETHOD(miibus_readreg,	arge_miibus_readreg),
+	DEVMETHOD(miibus_writereg,	arge_miibus_writereg),
+	DEVMETHOD(miibus_statchg,	arge_miibus_statchg),
+
+	{ 0, 0 }
+};
+
+static driver_t arge_driver = {
+	"arge",
+	arge_methods,
+	sizeof(struct arge_softc)
+};
+
+static devclass_t arge_devclass;
+
+DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
+DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
+
+/*
+ * Flushes all 
+ */
+static void
+arge_flush_ddr(struct arge_softc *sc)
+{
+
+	ATH_WRITE_REG(sc->arge_ddr_flush_reg, 1);
+	while (ATH_READ_REG(sc->arge_ddr_flush_reg) & 1)
+		;
+
+	ATH_WRITE_REG(sc->arge_ddr_flush_reg, 1);
+	while (ATH_READ_REG(sc->arge_ddr_flush_reg) & 1)
+		;
+}
+
+static int 
+arge_probe(device_t dev)
+{
+
+	device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
+	return (0);
+}
+
+static int
+arge_attach(device_t dev)
+{
+	uint8_t			eaddr[ETHER_ADDR_LEN];
+	struct ifnet		*ifp;
+	struct arge_softc	*sc;
+	int			error = 0, rid, phynum;
+	uint32_t		reg;
+
+	sc = device_get_softc(dev);
+	sc->arge_dev = dev;
+	sc->arge_mac_unit = device_get_unit(dev);
+
+	KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 
+	    ("if_arge: Only MAC0 and MAC1 supported"));
+	if (sc->arge_mac_unit == 0) {
+		sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE0;
+		sc->arge_pll_reg = AR71XX_PLL_ETH_INT0_CLK;
+	} else {
+		sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE1;
+		sc->arge_pll_reg = AR71XX_PLL_ETH_INT1_CLK;
+	}
+
+	/*
+	 *  Get which PHY of 5 available we should use for this unit
+	 */
+	if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
+	    "phy", &phynum) != 0) {
+		/*
+		 * Use port 4 (WAN) for GE0. For any other port use 
+		 * its PHY the same as its unit number 
+		 */
+		if (sc->arge_mac_unit == 0)
+			phynum = 4;
+		else
+			phynum = sc->arge_mac_unit;
+
+		device_printf(dev, "No PHY specified, using %d\n", phynum);
+	}
+
+	sc->arge_phy_num = phynum;
+
+
+	mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+	    MTX_DEF);
+	callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
+	TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
+
+	/* Map control/status registers. */
+	sc->arge_rid = 0;
+	sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 
+	    &sc->arge_rid, RF_ACTIVE);
+
+	if (sc->arge_res == NULL) {
+		device_printf(dev, "couldn't map memory\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	/* Allocate interrupts */
+	rid = 0;
+	sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 
+	    RF_SHAREABLE | RF_ACTIVE);
+
+	if (sc->arge_irq == NULL) {
+		device_printf(dev, "couldn't map interrupt\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	/* Allocate ifnet structure. */
+	ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
+
+	if (ifp == NULL) {
+		device_printf(dev, "couldn't allocate ifnet structure\n");
+		error = ENOSPC;
+		goto fail;
+	}
+
+	ifp->if_softc = sc;
+	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_ioctl = arge_ioctl;
+	ifp->if_start = arge_start;
+	ifp->if_init = arge_init;
+
+	/* XXX: add real size */
+	IFQ_SET_MAXLEN(&ifp->if_snd, 9);
+	ifp->if_snd.ifq_maxlen = 9;
+	IFQ_SET_READY(&ifp->if_snd);
+
+	ifp->if_capenable = ifp->if_capabilities;
+
+	eaddr[0] = 0x00;
+	eaddr[1] = 0x15;
+	eaddr[2] = 0x6d;
+	eaddr[3] = 0xc1;
+	eaddr[4] = 0x28;
+	eaddr[5] = 0x2e;
+
+	if (arge_dma_alloc(sc) != 0) {
+		error = ENXIO;
+		goto fail;
+	}
+
+	ARGE_WRITE(sc, AR71XX_MAC_CFG1, 
+		MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
+		MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
+
+	reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
+	reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
+	ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
+
+	ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
+
+	/* Reset MII bus */
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET);
+	DELAY(100);
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28);
+	DELAY(100);
+
+	/* 
+	 * Set all Ethernet address registers to the same initial values
+	 * set all four addresses to 66-88-aa-cc-dd-ee 
+	 */
+	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, 0x6dc1282e);
+	ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, 0x00000015);
+
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 
+	    FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
+
+	reg = FIFO_RX_FILTMATCH_ALL;
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, reg);
+
+	reg = FIFO_RX_FILTMASK_ALL;
+	reg &= ~FIFO_RX_FILTMASK_BYTE_MODE;
+	ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, reg);
+
+	/* Do MII setup. */
+	if (mii_phy_probe(dev, &sc->arge_miibus,
+	    arge_ifmedia_upd, arge_ifmedia_sts)) {
+		device_printf(dev, "MII without any phy!\n");
+		error = ENXIO;
+		goto fail;
+	}
+
+	/* Call MI attach routine. */
+	ether_ifattach(ifp, eaddr);
+
+	/* Hook interrupt last to avoid having to lock softc */
+	error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
+	    arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
+
+	if (error) {
+		device_printf(dev, "couldn't set up irq\n");
+		ether_ifdetach(ifp);
+		goto fail;
+	}
+
+fail:
+	if (error) 
+		arge_detach(dev);
+
+	return (error);
+}
+
+static int
+arge_detach(device_t dev)
+{
+	struct arge_softc		*sc = device_get_softc(dev);
+	struct ifnet		*ifp = sc->arge_ifp;
+
+	KASSERT(mtx_initialized(&sc->arge_mtx), ("arge mutex not initialized"));
+
+	/* These should only be active if attach succeeded */
+	if (device_is_attached(dev)) {
+		ARGE_LOCK(sc);
+		sc->arge_detach = 1;
+		arge_stop(sc);
+		ARGE_UNLOCK(sc);
+		taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
+		ether_ifdetach(ifp);
+	}
+
+	if (sc->arge_miibus)
+		device_delete_child(dev, sc->arge_miibus);
+	bus_generic_detach(dev);
+
+	if (sc->arge_intrhand)
+		bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
+
+	if (sc->arge_res)
+		bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 
+		    sc->arge_res);
+
+	if (ifp)
+		if_free(ifp);
+
+	arge_dma_free(sc);
+
+	mtx_destroy(&sc->arge_mtx);
+
+	return (0);
+
+}
+
+static int
+arge_suspend(device_t dev)
+{
+
+	panic("%s", __func__);
+	return 0;
+}
+
+static int
+arge_resume(device_t dev)
+{
+
+	panic("%s", __func__);
+	return 0;
+}
+
+static void
+arge_shutdown(device_t dev)
+{
+	struct arge_softc	*sc;
+
+	sc = device_get_softc(dev);
+
+	ARGE_LOCK(sc);
+	arge_stop(sc);
+	ARGE_UNLOCK(sc);
+}
+
+static int
+arge_miibus_readreg(device_t dev, int phy, int reg)
+{
+	struct arge_softc * sc = device_get_softc(dev);
+	int i, result;
+	uint32_t addr = 0x1000 | (phy << MAC_MII_PHY_ADDR_SHIFT) 
+	    | (reg & MAC_MII_REG_MASK);
+
+	if (phy != sc->arge_phy_num)
+		return (0);
+
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
+	ARGE_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
+
+	i = ARGE_MII_TIMEOUT;
+	while ((ARGE_READ(sc, AR71XX_MAC_MII_INDICATOR) & 
+	    MAC_MII_INDICATOR_BUSY) && (i--))
+		DELAY(5);
+
+	if (i < 0) {
+		dprintf("%s timedout\n", __func__);
+		/* XXX: return ERRNO istead? */
+		return (-1);
+	}
+
+	result = ARGE_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
+	dprintf("%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, 
+		 phy, reg, addr, result);
+
+	return (result);
+}
+
+static int
+arge_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+	struct arge_softc * sc = device_get_softc(dev);
+	int i;
+	uint32_t addr = 0x1000 
+	    | (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
+
+	dprintf("%s: phy=%d, reg=%02x, value=%04x\n", __func__, 
+	    phy, reg, data);
+
+	ARGE_WRITE(sc, AR71XX_MAC_MII_ADDR, addr);
+	ARGE_WRITE(sc, AR71XX_MAC_MII_CONTROL, data);
+
+	i = ARGE_MII_TIMEOUT;
+	while ((ARGE_READ(sc, AR71XX_MAC_MII_INDICATOR) & 
+	    MAC_MII_INDICATOR_BUSY) && (i--))
+		DELAY(5);
+
+	if (i < 0) {
+		dprintf("%s timedout\n", __func__);
+		/* XXX: return ERRNO istead? */
+		return (-1);
+	}
+
+	return (0);
+}
+
+static void
+arge_miibus_statchg(device_t dev)
+{
+	struct arge_softc		*sc;
+
+	sc = device_get_softc(dev);
+	taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
+}
+
+static void
+arge_link_task(void *arg, int pending)
+{
+	struct arge_softc	*sc;
+	struct mii_data		*mii;
+	struct ifnet		*ifp;
+	uint32_t		media;
+	uint32_t		cfg, ifcontrol, rx_filtmask, pll, sec_cfg;
+
+	sc = (struct arge_softc *)arg;
+
+	ARGE_LOCK(sc);
+	mii = device_get_softc(sc->arge_miibus);
+	ifp = sc->arge_ifp;
+	if (mii == NULL || ifp == NULL ||
+	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
+		ARGE_UNLOCK(sc);
+		return;
+	}
+
+	if (mii->mii_media_status & IFM_ACTIVE) {
+
+		media = IFM_SUBTYPE(mii->mii_media_active);
+
+		if (media != IFM_NONE) {
+			sc->arge_link_status = 1;
+
+			cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
+			ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
+			rx_filtmask = 
+			    ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
+			
+			cfg &= ~(MAC_CFG2_IFACE_MODE_1000 
+			    | MAC_CFG2_IFACE_MODE_10_100 
+			    | MAC_CFG2_FULL_DUPLEX);
+			ifcontrol &= ~MAC_IFCONTROL_SPEED;
+			rx_filtmask &= ~FIFO_RX_FILTMASK_BYTE_MODE;
+
+			switch(media) {
+			case IFM_10_T:
+				cfg |= MAC_CFG2_IFACE_MODE_10_100;
+				pll = PLL_ETH_INT_CLK_10;
+				break;
+			case IFM_100_TX:
+				cfg |= MAC_CFG2_IFACE_MODE_10_100;
+				ifcontrol |= MAC_IFCONTROL_SPEED;
+				pll = PLL_ETH_INT_CLK_100;
+				break;
+			case IFM_1000_T:
+			case IFM_1000_SX:
+				cfg |= MAC_CFG2_IFACE_MODE_1000;
+				rx_filtmask |= FIFO_RX_FILTMASK_BYTE_MODE;
+				pll = PLL_ETH_INT_CLK_1000;
+				break;
+			default:
+				pll = PLL_ETH_INT_CLK_100;
+				device_printf(sc->arge_dev, 
+				    "Unknown media %d\n", media);
+			}
+
+			ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD,
+			    0x008001ff);
+
+			ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
+			ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
+			ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 
+			    rx_filtmask);
+
+			/* set PLL registers */
+			sec_cfg = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG);
+			sec_cfg &= ~(3 << 17);
+			sec_cfg |= (2 << 17);
+
+			ATH_WRITE_REG(AR71XX_PLL_CPU_CONFIG, sec_cfg);
+			DELAY(100);
+
+			ATH_WRITE_REG(sc->arge_pll_reg, pll);
+
+			sec_cfg |= (3 << 17);
+			ATH_WRITE_REG(AR71XX_PLL_CPU_CONFIG, sec_cfg);
+			DELAY(100);
+
+			sec_cfg &= ~(3 << 17);
+			ATH_WRITE_REG(AR71XX_PLL_CPU_CONFIG, sec_cfg);
+			DELAY(100);
+		}
+	} else
+		sc->arge_link_status = 0;
+
+	ARGE_UNLOCK(sc);
+}
+
+static void
+arge_reset_dma(struct arge_softc *sc)
+{
+	unsigned int i;
+
+	ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
+	ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
+
+	ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
+	ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
+
+	/* Clear all possible RX interrupts */
+	for (i = 0; i < ARGE_RX_RING_COUNT; i++)
+		ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
+
+	/* 
+	 * Clear all possible TX interrupts
+	 */
+	for (i = 0; i < ARGE_TX_RING_COUNT; i++)
+		ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
+
+	/* 
+	 * Now Rx/Tx errors
+	 */
+	ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 
+	    DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
+	ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 
+	    DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
+}
+
+
+
+static void
+arge_init(void *xsc)
+{
+	struct arge_softc	 *sc = xsc;
+
+	ARGE_LOCK(sc);
+	arge_init_locked(sc);
+	ARGE_UNLOCK(sc);
+}
+
+static void
+arge_init_locked(struct arge_softc *sc)
+{
+	struct ifnet		*ifp = sc->arge_ifp;
+	struct mii_data		*mii;
+
+	ARGE_LOCK_ASSERT(sc);
+
+	mii = device_get_softc(sc->arge_miibus);
+
+	arge_stop(sc);
+
+	/* Init circular RX list. */
+	if (arge_rx_ring_init(sc) != 0) {
+		device_printf(sc->arge_dev,
+		    "initialization failed: no memory for rx buffers\n");
+		arge_stop(sc);
+		return;
+	}
+
+	/* Init tx descriptors. */
+	arge_tx_ring_init(sc);
+
+	arge_reset_dma(sc);
+
+	sc->arge_link_status = 0;
+	mii_mediachg(mii);
+
+	ifp->if_drv_flags |= IFF_DRV_RUNNING;
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+	callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
+	ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
+	ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
+
+	/* Start listening */
+	ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
+
+	/* Enable interrupts */
+	ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
+}
+
+/*
+ * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
+ * pointers to the fragment pointers.
+ */
+static int
+arge_encap(struct arge_softc *sc, struct mbuf **m_head)
+{
+	struct arge_txdesc	*txd;
+	struct arge_desc	*desc, *prev_desc;
+	bus_dma_segment_t	txsegs[ARGE_MAXFRAGS];
+	int			error, i, nsegs, prod, si, prev_prod;
+
+	ARGE_LOCK_ASSERT(sc);
+
+	prod = sc->arge_cdata.arge_tx_prod;
+	txd = &sc->arge_cdata.arge_txdesc[prod];
+	error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 
+	    txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
+
+	if (error == EFBIG) {
+		panic("EFBIG");
+	} else if (error != 0)
+		return (error);
+
+	if (nsegs == 0) {
+		m_freem(*m_head);
+		*m_head = NULL;
+		return (EIO);
+	}
+
+	/* Check number of available descriptors. */
+	if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
+		bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
+		return (ENOBUFS);
+	}
+
+	txd->tx_m = *m_head;
+	bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
+	    BUS_DMASYNC_PREWRITE);
+
+	si = prod;
+
+	/* 
+	 * Make a list of descriptors for this packet. DMA controller will
+	 * walk through it while arge_link is not zero.
+	 */
+	prev_prod = prod;
+	desc = prev_desc = NULL;
+	for (i = 0; i < nsegs; i++) {
+		desc = &sc->arge_rdata.arge_tx_ring[prod];
+		desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
+
+		desc->packet_addr = txsegs[i].ds_addr;
+		/* link with previous descriptor */
+		if (prev_desc)
+			prev_desc->packet_ctrl |= ARGE_DESC_MORE;
+
+		sc->arge_cdata.arge_tx_cnt++;
+		prev_desc = desc;
+		ARGE_INC(prod, ARGE_TX_RING_COUNT);
+	}
+
+	/* Update producer index. */
+	sc->arge_cdata.arge_tx_prod = prod;
+
+	/* Sync descriptors. */
+	bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
+	    sc->arge_cdata.arge_tx_ring_map,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	/* Start transmitting */
+	ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
+	return (0);
+}
+
+static void
+arge_start(struct ifnet *ifp)
+{
+	struct arge_softc	 *sc;
+
+	sc = ifp->if_softc;
+
+	ARGE_LOCK(sc);
+	arge_start_locked(ifp);
+	ARGE_UNLOCK(sc);
+}
+
+static void
+arge_start_locked(struct ifnet *ifp)
+{
+	struct arge_softc	*sc;
+	struct mbuf		*m_head;
+	int			enq;
+
+	sc = ifp->if_softc;
+
+	ARGE_LOCK_ASSERT(sc);
+
+	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
+	    IFF_DRV_RUNNING || sc->arge_link_status == 0 )
+		return;
+
+	arge_flush_ddr(sc);
+
+	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
+	    sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+		if (m_head == NULL)
+			break;
+
+		/*
+		 * Fix mbuf chain, all fragments should be 4 bytes aligned and
+		 * even 4 bytes
+		 */
+		arge_fix_chain(&m_head);
+
+		if (m_head == NULL) {
+			dprintf("failed to adjust mbuf chain\n");
+		}
+
+		/*
+		 * Pack the data into the transmit ring.
+		 */
+		if (arge_encap(sc, &m_head)) {
+			if (m_head == NULL)
+				break;
+			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
+			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			break;
+		}
+
+		enq++;
+		/*
+		 * If there's a BPF listener, bounce a copy of this frame
+		 * to him.
+		 */
+		ETHER_BPF_MTAP(ifp, m_head);
+	}
+}
+
+static void
+arge_stop(struct arge_softc *sc)
+{
+	struct ifnet	    *ifp;
+
+	ARGE_LOCK_ASSERT(sc);
+
+	ifp = sc->arge_ifp;
+	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	callout_stop(&sc->arge_stat_callout);
+
+	/* mask out interrupts */
+	ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
+
+	arge_reset_dma(sc);
+}
+
+
+static int
+arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
+{
+	struct arge_softc		*sc = ifp->if_softc;
+	struct ifreq		*ifr = (struct ifreq *) data;
+	struct mii_data		*mii;
+	int			error;
+
+	switch (command) {
+	case SIOCSIFFLAGS:
+		printf("Implement me: SIOCSIFFLAGS\n");
+		error = 0;
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		printf("Implement me: SIOCDELMULTI\n");
+		error = 0;
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		printf("Implement me: SIOCSIFMEDIA\n");
+		mii = device_get_softc(sc->arge_miibus);
+		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
+		break;
+	case SIOCSIFCAP:
+		error = 0;
+		ifp->if_hwassist = 0;
+		printf("Implement me: SIOCSIFCAP\n");
+		break;
+	default:
+		error = ether_ioctl(ifp, command, data);
+		break;
+	}
+
+	return (error);
+}
+
+/*
+ * Set media options.
+ */
+static int
+arge_ifmedia_upd(struct ifnet *ifp)
+{
+	struct arge_softc		*sc;
+	struct mii_data		*mii;
+	struct mii_softc	*miisc;
+	int			error;
+
+	sc = ifp->if_softc;
+	ARGE_LOCK(sc);
+	mii = device_get_softc(sc->arge_miibus);
+	if (mii->mii_instance) {
+		LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
+			mii_phy_reset(miisc);
+	}
+	error = mii_mediachg(mii);
+	ARGE_UNLOCK(sc);
+
+	return (error);
+}
+
+/*
+ * Report current media status.
+ */
+static void
+arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct arge_softc		*sc = ifp->if_softc;
+	struct mii_data		*mii;
+
+	mii = device_get_softc(sc->arge_miibus);
+	ARGE_LOCK(sc);
+	mii_pollstat(mii);
+	ARGE_UNLOCK(sc);
+	ifmr->ifm_active = mii->mii_media_active;
+	ifmr->ifm_status = mii->mii_media_status;
+}
+
+struct arge_dmamap_arg {
+	bus_addr_t	arge_busaddr;
+};
+
+static void
+arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+	struct arge_dmamap_arg	*ctx;
+
+	if (error != 0)
+		return;
+	ctx = arg;
+	ctx->arge_busaddr = segs[0].ds_addr;
+}
+
+static int
+arge_dma_alloc(struct arge_softc *sc)
+{
+	struct arge_dmamap_arg	ctx;
+	struct arge_txdesc	*txd;
+	struct arge_rxdesc	*rxd;
+	int			error, i;
+
+	/* Create parent DMA tag. */
+	error = bus_dma_tag_create(
+	    bus_get_dma_tag(sc->arge_dev),	/* parent */
+	    1, 0,			/* alignment, boundary */
+	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
+	    0,				/* nsegments */
+	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->arge_cdata.arge_parent_tag);
+	if (error != 0) {
+		device_printf(sc->arge_dev, "failed to create parent DMA tag\n");
+		goto fail;
+	}
+	/* Create tag for Tx ring. */
+	error = bus_dma_tag_create(
+	    sc->arge_cdata.arge_parent_tag,	/* parent */
+	    ARGE_RING_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    ARGE_TX_DMA_SIZE,		/* maxsize */
+	    1,				/* nsegments */
+	    ARGE_TX_DMA_SIZE,		/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->arge_cdata.arge_tx_ring_tag);
+	if (error != 0) {
+		device_printf(sc->arge_dev, "failed to create Tx ring DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Rx ring. */
+	error = bus_dma_tag_create(
+	    sc->arge_cdata.arge_parent_tag,	/* parent */
+	    ARGE_RING_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    ARGE_RX_DMA_SIZE,		/* maxsize */
+	    1,				/* nsegments */
+	    ARGE_RX_DMA_SIZE,		/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->arge_cdata.arge_rx_ring_tag);
+	if (error != 0) {
+		device_printf(sc->arge_dev, "failed to create Rx ring DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Tx buffers. */
+	error = bus_dma_tag_create(
+	    sc->arge_cdata.arge_parent_tag,	/* parent */
+	    sizeof(uint32_t), 0,	/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    MCLBYTES * ARGE_MAXFRAGS,	/* maxsize */
+	    ARGE_MAXFRAGS,		/* nsegments */
+	    MCLBYTES,			/* maxsegsize */
+	    0,				/* flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->arge_cdata.arge_tx_tag);
+	if (error != 0) {
+		device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Rx buffers. */
+	error = bus_dma_tag_create(
+	    sc->arge_cdata.arge_parent_tag,	/* parent */
+	    ARGE_RX_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***


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