svn commit: r257281 - in head/sys/arm: arm include
Zbigniew Bodek
zbb at FreeBSD.org
Mon Oct 28 21:39:56 UTC 2013
Author: zbb
Date: Mon Oct 28 21:39:54 2013
New Revision: 257281
URL: http://svnweb.freebsd.org/changeset/base/257281
Log:
Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
Modified:
head/sys/arm/arm/cpufunc.c
head/sys/arm/arm/cpufunc_asm_pj4b.S
head/sys/arm/arm/identcpu.c
head/sys/arm/include/armreg.h
head/sys/arm/include/cpufunc.h
Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c Mon Oct 28 21:37:45 2013 (r257280)
+++ head/sys/arm/arm/cpufunc.c Mon Oct 28 21:39:54 2013 (r257281)
@@ -541,65 +541,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
pj4bv7_setup /* cpu setup */
};
-
-struct cpu_functions pj4bv6_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- arm11_drain_writebuf, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* Domain */
- pj4b_setttb, /* Setttb */
- cpufunc_faultstatus, /* Faultstatus */
- cpufunc_faultaddress, /* Faultaddress */
-
- /* TLB functions */
-
- arm11_tlb_flushID, /* tlb_flushID */
- arm11_tlb_flushID_SE, /* tlb_flushID_SE */
- arm11_tlb_flushI, /* tlb_flushI */
- arm11_tlb_flushI_SE, /* tlb_flushI_SE */
- arm11_tlb_flushD, /* tlb_flushD */
- arm11_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
- armv6_icache_sync_all, /* icache_sync_all */
- pj4b_icache_sync_range, /* icache_sync_range */
-
- armv6_dcache_wbinv_all, /* dcache_wbinv_all */
- pj4b_dcache_wbinv_range, /* dcache_wbinv_range */
- pj4b_dcache_inv_range, /* dcache_inv_range */
- pj4b_dcache_wb_range, /* dcache_wb_range */
-
- armv6_idcache_wbinv_all, /* idcache_wbinv_all */
- pj4b_idcache_wbinv_range, /* idcache_wbinv_all */
-
- (void *)cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- pj4b_drain_readbuf, /* flush_prefetchbuf */
- arm11_drain_writebuf, /* drain_writebuf */
- pj4b_flush_brnchtgt_all, /* flush_brnchtgt_C */
- pj4b_flush_brnchtgt_va, /* flush_brnchtgt_E */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
-
- cpufunc_null_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- arm11_context_switch, /* context_switch */
-
- pj4bv6_setup /* cpu setup */
-};
#endif /* CPU_MV_PJ4B */
#ifdef CPU_SA110
@@ -1497,27 +1438,14 @@ set_cpufuncs()
#endif /* CPU_CORTEXA */
#if defined(CPU_MV_PJ4B)
- if (cputype == CPU_ID_MV88SV581X_V6 ||
- cputype == CPU_ID_MV88SV581X_V7 ||
+ if (cputype == CPU_ID_MV88SV581X_V7 ||
cputype == CPU_ID_MV88SV584X_V7 ||
- cputype == CPU_ID_ARM_88SV581X_V6 ||
cputype == CPU_ID_ARM_88SV581X_V7) {
- if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK)
- cpufuncs = pj4bv7_cpufuncs;
- else
- cpufuncs = pj4bv6_cpufuncs;
-
- get_cachetype_cp15();
- pmap_pte_init_mmu_v6();
- goto out;
- } else if (cputype == CPU_ID_ARM_88SV584X_V6 ||
- cputype == CPU_ID_MV88SV584X_V6) {
- cpufuncs = pj4bv6_cpufuncs;
+ cpufuncs = pj4bv7_cpufuncs;
get_cachetype_cp15();
pmap_pte_init_mmu_v6();
goto out;
}
-
#endif /* CPU_MV_PJ4B */
#ifdef CPU_SA110
if (cputype == CPU_ID_SA110) {
@@ -2447,44 +2375,6 @@ arm11x6_setup(char *args)
#ifdef CPU_MV_PJ4B
void
-pj4bv6_setup(char *args)
-{
- int cpuctrl;
-
- pj4b_config();
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE;
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
- cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
- cpuctrl |= CPU_CONTROL_DC_ENABLE;
- cpuctrl |= (0xf << 3);
-#ifdef __ARMEB__
- cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
- cpuctrl |= CPU_CONTROL_SYST_ENABLE;
- cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
- cpuctrl |= CPU_CONTROL_IC_ENABLE;
- if (vector_page == ARM_VECTORS_HIGH)
- cpuctrl |= CPU_CONTROL_VECRELOC;
- cpuctrl |= (0x5 << 16);
- cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
- /* XXX not yet */
- /* cpuctrl |= CPU_CONTROL_L2_ENABLE; */
-
- /* Make sure caches are clean. */
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
-
- /* Set the control register */
- ctrl = cpuctrl;
- cpu_control(0xffffffff, cpuctrl);
-
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
-}
-
-void
pj4bv7_setup(args)
char *args;
{
Modified: head/sys/arm/arm/cpufunc_asm_pj4b.S
==============================================================================
--- head/sys/arm/arm/cpufunc_asm_pj4b.S Mon Oct 28 21:37:45 2013 (r257280)
+++ head/sys/arm/arm/cpufunc_asm_pj4b.S Mon Oct 28 21:39:54 2013 (r257281)
@@ -34,9 +34,6 @@ __FBSDID("$FreeBSD$");
#include <machine/param.h>
-.Lpj4b_cache_line_size:
- .word _C_LABEL(arm_pdcache_line_size)
-
.Lpj4b_sf_ctrl_reg:
.word 0xf1021820
@@ -52,135 +49,6 @@ ENTRY(pj4b_setttb)
RET
END(pj4b_setttb)
-ENTRY_NP(armv6_icache_sync_all)
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache cleaning code.
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
- mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(armv6_icache_sync_all)
-
-ENTRY(pj4b_icache_sync_range)
- sub r1, r1, #1
- add r1, r0, r1
- mcrr p15, 0, r1, r0, c5 /* invalidate IC range */
- mcrr p15, 0, r1, r0, c12 /* clean DC range */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_icache_sync_range)
-
-ENTRY(pj4b_dcache_inv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */
-1:
- mcr p15, 0, r0, c7, c6, 1
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_dcache_inv_range)
-
-ENTRY(armv6_idcache_wbinv_all)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */
- mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(armv6_idcache_wbinv_all)
-
-ENTRY(armv6_dcache_wbinv_all)
- mov r0, #0
- mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(armv6_dcache_wbinv_all)
-
-ENTRY(pj4b_idcache_wbinv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
-1:
-#ifdef SMP
- /* Request for ownership */
- ldr r2, [r0]
- str r2, [r0]
-#endif
- mcr p15, 0, r0, c7, c5, 1
- mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_idcache_wbinv_range)
-
-ENTRY(pj4b_dcache_wbinv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
-1:
-#ifdef SMP
- /* Request for ownership */
- ldr r2, [r0]
- str r2, [r0]
-#endif
- mcr p15, 0, r0, c7, c14, 1
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_dcache_wbinv_range)
-
-ENTRY(pj4b_dcache_wb_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
-1:
-#ifdef SMP
- /* Request for ownership */
- ldr r2, [r0]
- str r2, [r0]
-#endif
- mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_dcache_wb_range)
-
ENTRY(pj4b_drain_readbuf)
mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
RET
Modified: head/sys/arm/arm/identcpu.c
==============================================================================
--- head/sys/arm/arm/identcpu.c Mon Oct 28 21:37:45 2013 (r257280)
+++ head/sys/arm/arm/identcpu.c Mon Oct 28 21:39:54 2013 (r257281)
@@ -323,18 +323,10 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD",
generic_steppings },
- { CPU_ID_MV88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
- generic_steppings },
- { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
- generic_steppings },
{ CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
generic_steppings },
{ CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
generic_steppings },
- { CPU_ID_MV88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
- generic_steppings },
- { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
- generic_steppings },
{ CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
generic_steppings },
Modified: head/sys/arm/include/armreg.h
==============================================================================
--- head/sys/arm/include/armreg.h Mon Oct 28 21:37:45 2013 (r257280)
+++ head/sys/arm/include/armreg.h Mon Oct 28 21:39:54 2013 (r257281)
@@ -173,14 +173,10 @@
#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
#endif
-#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */
#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
-#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */
#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
/* Marvell's CPUIDs with ARM ID in implementor field */
-#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
-#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */
#define CPU_ID_FA526 0x66015260
#define CPU_ID_FA626TE 0x66056260
Modified: head/sys/arm/include/cpufunc.h
==============================================================================
--- head/sys/arm/include/cpufunc.h Mon Oct 28 21:37:45 2013 (r257280)
+++ head/sys/arm/include/cpufunc.h Mon Oct 28 21:39:54 2013 (r257281)
@@ -482,14 +482,6 @@ void arm11_drain_writebuf (void);
void pj4b_setttb (u_int);
-void pj4b_icache_sync_range (vm_offset_t, vm_size_t);
-
-void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t);
-void pj4b_dcache_inv_range (vm_offset_t, vm_size_t);
-void pj4b_dcache_wb_range (vm_offset_t, vm_size_t);
-
-void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t);
-
void pj4b_drain_readbuf (void);
void pj4b_flush_brnchtgt_all (void);
void pj4b_flush_brnchtgt_va (u_int);
@@ -523,7 +515,6 @@ void armv7_drain_writebuf (void);
void armv7_sev (void);
u_int armv7_auxctrl (u_int, u_int);
void pj4bv7_setup (char *string);
-void pj4bv6_setup (char *string);
void pj4b_config (void);
int get_core_id (void);
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