svn commit: r212306 - head/sys/dev/mii
Pyun YongHyeon
yongari at FreeBSD.org
Tue Sep 7 22:44:30 UTC 2010
Author: yongari
Date: Tue Sep 7 22:44:29 2010
New Revision: 212306
URL: http://svn.freebsd.org/changeset/base/212306
Log:
Remove trailing CR at EOL.
Modified:
head/sys/dev/mii/brgphyreg.h
Modified: head/sys/dev/mii/brgphyreg.h
==============================================================================
--- head/sys/dev/mii/brgphyreg.h Tue Sep 7 22:40:45 2010 (r212305)
+++ head/sys/dev/mii/brgphyreg.h Tue Sep 7 22:44:29 2010 (r212306)
@@ -262,103 +262,103 @@
#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */
#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */
-/*******************************************************/
-/* Begin: Shared SerDes PHY register definitions */
-/*******************************************************/
-
-/* SerDes autoneg is different from copper */
-#define BRGPHY_SERDES_ANAR 0x04
-#define BRGPHY_SERDES_ANAR_FDX 0x0020
-#define BRGPHY_SERDES_ANAR_HDX 0x0040
-#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
-#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
-#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
-#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
-
-#define BRGPHY_SERDES_ANLPAR 0x05
-#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
-#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
-#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
-#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
-#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
-#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
-
-/*******************************************************/
-/* End: Shared SerDes PHY register definitions */
-/*******************************************************/
-
-/*******************************************************/
-/* Begin: PHY register values for the 5706 PHY */
-/*******************************************************/
-
-/*
- * Shadow register 0x1C, bit 15 is write enable,
- * bits 14-10 select function (0x00 to 0x1F).
- */
-#define BRGPHY_MII_SHADOW_1C 0x1C
+/*******************************************************/
+/* Begin: Shared SerDes PHY register definitions */
+/*******************************************************/
+
+/* SerDes autoneg is different from copper */
+#define BRGPHY_SERDES_ANAR 0x04
+#define BRGPHY_SERDES_ANAR_FDX 0x0020
+#define BRGPHY_SERDES_ANAR_HDX 0x0040
+#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7)
+#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7)
+#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7)
+#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7)
+
+#define BRGPHY_SERDES_ANLPAR 0x05
+#define BRGPHY_SERDES_ANLPAR_FDX 0x0020
+#define BRGPHY_SERDES_ANLPAR_HDX 0x0040
+#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7)
+#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7)
+#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7)
+#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7)
+
+/*******************************************************/
+/* End: Shared SerDes PHY register definitions */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5706 PHY */
+/*******************************************************/
+
+/*
+ * Shadow register 0x1C, bit 15 is write enable,
+ * bits 14-10 select function (0x00 to 0x1F).
+ */
+#define BRGPHY_MII_SHADOW_1C 0x1C
#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000
#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00
-
+
/* Shadow 0x1C Mode Control Register (select value 0x1F) */
#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10)
/* When set, Regs 0-0x0F are 1000X, else 1000T */
-#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
+#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001
#define BRGPHY_MII_TEST1 0x1E
#define BRGPHY_TEST1_TRIM_EN 0x0010
#define BRGPHY_TEST1_CRC_EN 0x8000
#define BRGPHY_MII_TEST2 0x1F
-
-/*******************************************************/
-/* End: PHY register values for the 5706 PHY */
-/*******************************************************/
-
-/*******************************************************/
-/* Begin: PHY register values for the 5708S SerDes PHY */
-/*******************************************************/
-
-/* Autoneg Next Page Transmit 1 Regiser */
-#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
-#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
-
-/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
-#define BRGPHY_5708S_BLOCK_ADDR 0x1f
+
+/*******************************************************/
+/* End: PHY register values for the 5706 PHY */
+/*******************************************************/
+
+/*******************************************************/
+/* Begin: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
+
+/* Autoneg Next Page Transmit 1 Regiser */
+#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B
+#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001
+
+/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */
+#define BRGPHY_5708S_BLOCK_ADDR 0x1f
#define BRGPHY_5708S_DIG_PG0 0x0000
#define BRGPHY_5708S_DIG3_PG2 0x0002
#define BRGPHY_5708S_TX_MISC_PG5 0x0005
-
-/* 5708S SerDes "Digital" Registers (page 0) */
-#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
-#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
-#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
-
-#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
-#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
-#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
-#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
-
-
-#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
-#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
-
-/* 5708S SerDes "Digital 3" Registers (page 2) */
-#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
-#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
-
-/* 5708S SerDes "TX Misc" Registers (page 5) */
-#define BRGPHY_5708S_PG5_2500STATUS1 0x10
-#define BRGPHY_5708S_PG5_TXACTL1 0x15
-#define BRGPHY_5708S_PG5_TXACTL3 0x17
-
-/*******************************************************/
-/* End: PHY register values for the 5708S SerDes PHY */
-/*******************************************************/
-
+
+/* 5708S SerDes "Digital" Registers (page 0) */
+#define BRGPHY_5708S_PG0_1000X_CTL1 0x10
+#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010
+#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001
+
+#define BRGPHY_5708S_PG0_1000X_STAT1 0x14
+#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002
+#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3)
+#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3)
+
+
+#define BRGPHY_5708S_PG0_1000X_CTL2 0x11
+#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001
+
+/* 5708S SerDes "Digital 3" Registers (page 2) */
+#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10
+#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001
+
+/* 5708S SerDes "TX Misc" Registers (page 5) */
+#define BRGPHY_5708S_PG5_2500STATUS1 0x10
+#define BRGPHY_5708S_PG5_TXACTL1 0x15
+#define BRGPHY_5708S_PG5_TXACTL3 0x17
+
+/*******************************************************/
+/* End: PHY register values for the 5708S SerDes PHY */
+/*******************************************************/
+
/*******************************************************/
/* Begin: PHY register values for the 5709S SerDes PHY */
/*******************************************************/
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