svn commit: r201468 - in head/sys: arm/arm arm/conf arm/econa
arm/include conf
Rui Paulo
rpaulo at FreeBSD.org
Mon Jan 4 03:35:46 UTC 2010
Author: rpaulo
Date: Mon Jan 4 03:35:45 2010
New Revision: 201468
URL: http://svn.freebsd.org/changeset/base/201468
Log:
Add support for Cavium Econa CNS11XX ARM boards. These boards were
previously know by StarSemi STR9104.
Tested by the submitter on an Emprex NSD-100 board.
Submitted by: Yohanes Nugroho <yohanes at gmail.com>
Reviewed by: freebsd-arm, stas
Obtained from: //depot/projects/str91xx/...
Added:
head/sys/arm/arm/cpufunc_asm_fa526.S (contents, props changed)
head/sys/arm/conf/CNS11XXNAS (contents, props changed)
head/sys/arm/conf/CNS11XXNAS.hints (contents, props changed)
head/sys/arm/econa/
head/sys/arm/econa/cfi_bus_econa.c (contents, props changed)
head/sys/arm/econa/econa.c (contents, props changed)
head/sys/arm/econa/econa_machdep.c (contents, props changed)
head/sys/arm/econa/econa_reg.h (contents, props changed)
head/sys/arm/econa/econa_var.h (contents, props changed)
head/sys/arm/econa/ehci_ebus.c (contents, props changed)
head/sys/arm/econa/files.econa (contents, props changed)
head/sys/arm/econa/if_ece.c (contents, props changed)
head/sys/arm/econa/if_ecereg.h (contents, props changed)
head/sys/arm/econa/if_ecevar.h (contents, props changed)
head/sys/arm/econa/ohci_ec.c (contents, props changed)
head/sys/arm/econa/std.econa (contents, props changed)
head/sys/arm/econa/timer.c (contents, props changed)
head/sys/arm/econa/uart_bus_ec.c (contents, props changed)
head/sys/arm/econa/uart_cpu_ec.c (contents, props changed)
Modified:
head/sys/arm/arm/cpufunc.c
head/sys/arm/arm/elf_trampoline.c
head/sys/arm/include/cpuconf.h
head/sys/arm/include/cpufunc.h
head/sys/conf/Makefile.arm
head/sys/conf/options.arm
Modified: head/sys/arm/arm/cpufunc.c
==============================================================================
--- head/sys/arm/arm/cpufunc.c Mon Jan 4 01:52:15 2010 (r201467)
+++ head/sys/arm/arm/cpufunc.c Mon Jan 4 03:35:45 2010 (r201468)
@@ -781,6 +781,73 @@ struct cpu_functions xscalec3_cpufuncs =
xscale_setup /* cpu setup */
};
#endif /* CPU_XSCALE_81342 */
+
+
+#if defined(CPU_FA526)
+struct cpu_functions fa526_cpufuncs = {
+ /* CPU functions */
+
+ .cf_id = cpufunc_id,
+ .cf_cpwait = cpufunc_nullop,
+
+ /* MMU functions */
+
+ .cf_control = cpufunc_control,
+ .cf_domains = cpufunc_domains,
+ .cf_setttb = fa526_setttb,
+ .cf_faultstatus = cpufunc_faultstatus,
+ .cf_faultaddress = cpufunc_faultaddress,
+
+ /* TLB functions */
+
+ .cf_tlb_flushID = armv4_tlb_flushID,
+ .cf_tlb_flushID_SE = fa526_tlb_flushID_SE,
+ .cf_tlb_flushI = armv4_tlb_flushI,
+ .cf_tlb_flushI_SE = fa526_tlb_flushI_SE,
+ .cf_tlb_flushD = armv4_tlb_flushD,
+ .cf_tlb_flushD_SE = armv4_tlb_flushD_SE,
+
+ /* Cache operations */
+
+ .cf_icache_sync_all = fa526_icache_sync_all,
+ .cf_icache_sync_range = fa526_icache_sync_range,
+
+ .cf_dcache_wbinv_all = fa526_dcache_wbinv_all,
+ .cf_dcache_wbinv_range = fa526_dcache_wbinv_range,
+ .cf_dcache_inv_range = fa526_dcache_inv_range,
+ .cf_dcache_wb_range = fa526_dcache_wb_range,
+
+ .cf_idcache_wbinv_all = fa526_idcache_wbinv_all,
+ .cf_idcache_wbinv_range = fa526_idcache_wbinv_range,
+
+
+ .cf_l2cache_wbinv_all = cpufunc_nullop,
+ .cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_inv_range = (void *)cpufunc_nullop,
+ .cf_l2cache_wb_range = (void *)cpufunc_nullop,
+
+
+ /* Other functions */
+
+ .cf_flush_prefetchbuf = fa526_flush_prefetchbuf,
+ .cf_drain_writebuf = armv4_drain_writebuf,
+ .cf_flush_brnchtgt_C = cpufunc_nullop,
+ .cf_flush_brnchtgt_E = fa526_flush_brnchtgt_E,
+
+ .cf_sleep = fa526_cpu_sleep,
+
+ /* Soft functions */
+
+ .cf_dataabt_fixup = cpufunc_null_fixup,
+ .cf_prefetchabt_fixup = cpufunc_null_fixup,
+
+ .cf_context_switch = fa526_context_switch,
+
+ .cf_setup = fa526_setup
+};
+#endif /* CPU_FA526 */
+
+
/*
* Global constants also used by locore.s
*/
@@ -793,6 +860,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /*
defined (CPU_ARM9E) || defined (CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
+ defined(CPU_FA526) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
static void get_cachetype_cp15(void);
@@ -1073,6 +1141,19 @@ set_cpufuncs()
goto out;
}
#endif /* CPU_SA1110 */
+#ifdef CPU_FA526
+ if (cputype == CPU_ID_FA526) {
+ cpufuncs = fa526_cpufuncs;
+ cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
+ get_cachetype_cp15();
+ pmap_pte_init_generic();
+
+ /* Use powersave on this CPU. */
+ cpu_do_powersave = 1;
+
+ goto out;
+ }
+#endif /* CPU_FA526 */
#ifdef CPU_IXP12X0
if (cputype == CPU_ID_IXP1200) {
cpufuncs = ixp12x0_cpufuncs;
@@ -1547,7 +1628,8 @@ late_abort_fixup(arg)
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
- defined(CPU_ARM10) || defined(CPU_ARM11)
+ defined(CPU_ARM10) || defined(CPU_ARM11) || \
+ defined(CPU_FA526)
#define IGN 0
#define OR 1
@@ -2013,6 +2095,62 @@ sa11x0_setup(args)
}
#endif /* CPU_SA1100 || CPU_SA1110 */
+#if defined(CPU_FA526)
+struct cpu_option fa526_options[] = {
+#ifdef COMPAT_12
+ { "nocache", IGN, BIC, (CPU_CONTROL_IC_ENABLE |
+ CPU_CONTROL_DC_ENABLE) },
+ { "nowritebuf", IGN, BIC, CPU_CONTROL_WBUF_ENABLE },
+#endif /* COMPAT_12 */
+ { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
+ CPU_CONTROL_DC_ENABLE) },
+ { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE |
+ CPU_CONTROL_DC_ENABLE) },
+ { "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
+ { "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
+ { NULL, IGN, IGN, 0 }
+};
+
+void
+fa526_setup(char *args)
+{
+ int cpuctrl, cpuctrlmask;
+
+ cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
+ | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_LABT_ENABLE;
+ cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_32BP_ENABLE
+ | CPU_CONTROL_32BD_ENABLE | CPU_CONTROL_SYST_ENABLE
+ | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+ | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
+ | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+ | CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_BPRD_ENABLE
+ | CPU_CONTROL_CPCLK | CPU_CONTROL_VECRELOC;
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+ cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+ cpuctrl = parse_cpu_options(args, fa526_options, cpuctrl);
+
+#ifdef __ARMEB__
+ cpuctrl |= CPU_CONTROL_BEND_ENABLE;
+#endif
+
+ if (vector_page == ARM_VECTORS_HIGH)
+ cpuctrl |= CPU_CONTROL_VECRELOC;
+
+ /* Clear out the cache */
+ cpu_idcache_wbinv_all();
+
+ /* Set the control register */
+ ctrl = cpuctrl;
+ cpu_control(0xffffffff, cpuctrl);
+}
+#endif /* CPU_FA526 */
+
+
#if defined(CPU_IXP12X0)
struct cpu_option ixp12x0_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
Added: head/sys/arm/arm/cpufunc_asm_fa526.S
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/arm/cpufunc_asm_fa526.S Mon Jan 4 03:35:45 2010 (r201468)
@@ -0,0 +1,209 @@
+/* $NetBSD: cpufunc_asm_fa526.S,v 1.3 2008/10/15 16:56:49 matt Exp $*/
+/*-
+ * Copyright (c) 2008 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas <matt at 3am-software.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <machine/asm.h>
+__FBSDID("$FreeBSD$");
+
+#define CACHELINE_SIZE 16
+
+ENTRY(fa526_setttb)
+ mov r1, #0
+ mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
+ mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
+ mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
+ mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
+
+ mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
+
+ /* If we have updated the TTB we must flush the TLB */
+ mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
+
+ /* Make sure that pipeline is emptied */
+ mov r0, r0
+ mov r0, r0
+ mov pc, lr
+
+/*
+ * TLB functions
+ */
+ENTRY(fa526_tlb_flushID_SE)
+ mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
+ mov pc, lr
+
+/*
+ * TLB functions
+ */
+ENTRY(fa526_tlb_flushI_SE)
+ mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */
+ mov pc, lr
+
+ENTRY(fa526_cpu_sleep)
+ mov r0, #0
+/* nop
+ nop*/
+ mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
+ mov pc, lr
+
+ENTRY(fa526_flush_prefetchbuf)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 4 /* Pre-fetch flush */
+ mov pc, lr
+
+/*
+ * Cache functions
+ */
+ENTRY(fa526_idcache_wbinv_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
+ mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mov pc, lr
+
+ENTRY(fa526_icache_sync_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
+ mov pc, lr
+
+ENTRY(fa526_dcache_wbinv_all)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
+ mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mov pc, lr
+
+/*
+ * Soft functions
+ */
+ENTRY(fa526_dcache_wbinv_range)
+ cmp r1, #0x4000
+ bhs _C_LABEL(fa526_dcache_wbinv_all)
+
+ and r2, r0, #(CACHELINE_SIZE - 1)
+ add r1, r1, r2
+ bic r0, r0, #(CACHELINE_SIZE - 1)
+
+1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
+ add r0, r0, #CACHELINE_SIZE
+ subs r1, r1, #CACHELINE_SIZE
+ bhi 1b
+
+ mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mov pc, lr
+
+ENTRY(fa526_dcache_wb_range)
+ cmp r1, #0x4000
+ bls 1f
+
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 0 /* clean entire D$ */
+ b 3f
+
+1: and r2, r0, #(CACHELINE_SIZE - 1)
+ add r1, r1, r2
+ bic r0, r0, #(CACHELINE_SIZE - 1)
+
+2: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
+ add r0, r0, #CACHELINE_SIZE
+ subs r1, r1, #CACHELINE_SIZE
+ bhi 2b
+
+3: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mov pc, lr
+
+ENTRY(fa526_dcache_inv_range)
+ and r2, r0, #(CACHELINE_SIZE - 1)
+ add r1, r1, r2
+ bic r0, r0, #(CACHELINE_SIZE - 1)
+
+1: mcr p15, 0, r0, c7, c6, 1 /* invalidate D$ single entry */
+ add r0, r0, #CACHELINE_SIZE
+ subs r1, r1, #CACHELINE_SIZE
+ bhi 1b
+
+ mov pc, lr
+
+ENTRY(fa526_idcache_wbinv_range)
+ cmp r1, #0x4000
+ bhs _C_LABEL(fa526_idcache_wbinv_all)
+
+ and r2, r0, #(CACHELINE_SIZE - 1)
+ add r1, r1, r2
+ bic r0, r0, #(CACHELINE_SIZE - 1)
+
+1: mcr p15, 0, r0, c7, c14, 1 /* clean and invalidate D$ entry */
+ mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
+ add r0, r0, #CACHELINE_SIZE
+ subs r1, r1, #CACHELINE_SIZE
+ bhi 1b
+
+2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mov pc, lr
+
+ENTRY(fa526_icache_sync_range)
+ cmp r1, #0x4000
+ bhs _C_LABEL(fa526_icache_sync_all)
+
+ and r2, r0, #(CACHELINE_SIZE - 1)
+ add r1, r1, r2
+ bic r0, r0, #(CACHELINE_SIZE - 1)
+
+1: mcr p15, 0, r0, c7, c10, 1 /* clean D$ entry */
+ mcr p15, 0, r0, c7, c5, 1 /* invalidate I$ entry */
+ add r0, r0, #CACHELINE_SIZE
+ subs r1, r1, #CACHELINE_SIZE
+ bhi 1b
+
+2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
+ mov pc, lr
+
+ENTRY(fa526_flush_brnchtgt_E)
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB cache */
+ mov pc, lr
+
+ENTRY(fa526_context_switch)
+ /*
+ * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
+ * Thus the data cache will contain only kernel data and the
+ * instruction cache will contain only kernel code, and all
+ * kernel mappings are shared by all processes.
+ */
+
+ mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
+
+ /* If we have updated the TTB we must flush the TLB */
+ mov r0, #0
+ mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
+
+ /* Make sure that pipeline is emptied */
+ mov r0, r0
+ mov r0, r0
+ mov pc, lr
+
Modified: head/sys/arm/arm/elf_trampoline.c
==============================================================================
--- head/sys/arm/arm/elf_trampoline.c Mon Jan 4 01:52:15 2010 (r201467)
+++ head/sys/arm/arm/elf_trampoline.c Mon Jan 4 03:35:45 2010 (r201468)
@@ -57,6 +57,8 @@ void __startC(void);
#define cpu_idcache_wbinv_all arm8_cache_purgeID
#elif defined(CPU_ARM9)
#define cpu_idcache_wbinv_all arm9_idcache_wbinv_all
+#elif defined(CPU_FA526)
+#define cpu_idcache_wbinv_all fa526_idcache_wbinv_all
#elif defined(CPU_ARM9E)
#define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all
#elif defined(CPU_ARM10)
Added: head/sys/arm/conf/CNS11XXNAS
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/CNS11XXNAS Mon Jan 4 03:35:45 2010 (r201468)
@@ -0,0 +1,126 @@
+# CNS11XXNAS - StarSemi STR9104/Cavium CNS1102 NAS
+# kernel configuration file for FreeBSD/arm
+#
+# For more information on this file, please read the handbook section on
+# Kernel Configuration Files:
+#
+# http://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
+#
+# The handbook is also available locally in /usr/share/doc/handbook
+# if you've installed the doc distribution, otherwise always see the
+# FreeBSD World Wide Web server (http://www.FreeBSD.org/) for the
+# latest information.
+#
+# An exhaustive list of options and more detailed explanations of the
+# device lines is also present in the ../../conf/NOTES and NOTES files.
+# If you are in doubt as to the purpose or necessity of a line, check first
+# in NOTES.
+#
+# $FreeBSD$
+
+ident CNS11XXNAS
+
+#options PHYSADDR=0x10000000
+#options KERNPHYSADDR=0x10200000
+#options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm
+#options FLASHADDR=0x50000000
+#options LOADERRAMADDR=0x00000000
+#options STARTUP_PAGETABLE_ADDR=0x10000000
+
+include "../econa/std.econa"
+
+#To statically compile in device wiring instead of /boot/device.hints
+hints "CNS11XXNAS.hints"
+makeoptions MODULES_OVERRIDE=""
+
+makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
+options HZ=100
+options DEVICE_POLLING
+
+# Debugging for use in -current
+options KDB
+#options GDB
+options DDB #Enable the kernel debugger
+#options INVARIANTS #Enable calls of extra sanity checking
+#options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
+#options WITNESS #Enable checks to detect deadlocks and cycles
+##options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
+#options DIAGNOSTIC
+
+
+#options COMPAT_FREEBSD5
+#options COMPAT_FREEBSD6
+#options COMPAT_FREEBSD7
+
+
+options SCHED_ULE #ULE scheduler
+#options SCHED_4BSD #4BSD scheduler
+options GEOM_PART_GPT # GUID Partition Tables.
+#options GEOM_PART_EBR
+#options GEOM_PART_EBR_COMPAT
+options GEOM_LABEL # Provides labelization
+
+
+options INET #InterNETworking
+options INET6 #IPv6 communications protocols
+options FFS #Berkeley Fast Filesystem
+options SOFTUPDATES #Enable FFS soft updates support
+options UFS_ACL #Support for access control lists
+options UFS_DIRHASH #Improve performance on big directories
+options NFSCLIENT #Network Filesystem Client
+#options NFSSERVER #Network Filesystem Server
+#options NFSLOCKD #Network Lock Manager
+options NFS_ROOT #NFS usable as /, requires NFSCLIENT
+options MSDOSFS #MSDOS Filesystem
+#options CD9660 #ISO 9660 Filesystem
+#options PROCFS #Process filesystem (requires PSEUDOFS)
+options PSEUDOFS #Pseudo-filesystem framework
+options SCSI_DELAY=5000 #Delay (in ms) before probing SCSI
+options KTRACE #ktrace(1) support
+options SYSVSHM #SYSV-style shared memory
+options SYSVMSG #SYSV-style message queues
+options SYSVSEM #SYSV-style semaphores
+options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
+options MUTEX_NOINLINE #Mutex inlines are space hogs
+options RWLOCK_NOINLINE #rwlock inlines are space hogs
+options SX_NOINLINE #sx inliens are space hogs
+#options BOOTP
+#options BOOTP_NFSROOT
+#options BOOTP_NFSV3
+#options BOOTP_WIRED_TO=npe0
+#options BOOTP_COMPAT
+
+#device pci
+device uart
+
+
+device firmware
+device mii # Minimal mii routines
+device ether
+device bpf
+
+device pty
+device loop
+
+device md
+device random # Entropy device
+
+#options ARM_USE_SMALL_ALLOC
+
+device usb
+#options USB_DEBUG
+device ohci
+device ehci
+device umass
+device scbus # SCSI bus (required for SCSI)
+device da # Direct Access (disks)
+device pass
+device cfi
+
+#device udav # Davicom DM9601E USB
+
+device geom_label
+device geom_journal
+device geom_part_bsd
+
+options ROOTDEVNAME=\"ufs:da0s1a\"
Added: head/sys/arm/conf/CNS11XXNAS.hints
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/CNS11XXNAS.hints Mon Jan 4 03:35:45 2010 (r201468)
@@ -0,0 +1 @@
+# $FreeBSD$
Added: head/sys/arm/econa/cfi_bus_econa.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/econa/cfi_bus_econa.c Mon Jan 4 03:35:45 2010 (r201468)
@@ -0,0 +1,67 @@
+/*-
+ * Copyright (c) 2009 Yohanes Nugroho <yohanes at gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/conf.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <sys/sysctl.h>
+
+#include <machine/bus.h>
+
+#include <dev/cfi/cfi_var.h>
+
+#include <arm/econa/econa_reg.h>
+#include <arm/econa/econa_var.h>
+
+static int
+cfi_econa_probe(device_t dev)
+{
+
+ return cfi_probe(dev);
+}
+
+static device_method_t cfi_econa_methods[] = {
+ /* device interface */
+ DEVMETHOD(device_probe, cfi_econa_probe),
+ DEVMETHOD(device_attach, cfi_attach),
+ DEVMETHOD(device_detach, cfi_detach),
+
+ {0, 0}
+};
+
+static driver_t cfi_econa_driver = {
+ cfi_driver_name,
+ cfi_econa_methods,
+ sizeof(struct cfi_softc),
+};
+DRIVER_MODULE(cfi, econaarm, cfi_econa_driver, cfi_devclass, 0, 0);
Added: head/sys/arm/econa/econa.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/econa/econa.c Mon Jan 4 03:35:45 2010 (r201468)
@@ -0,0 +1,758 @@
+/*-
+ * Copyright (c) 2009 Yohanes Nugroho <yohanes at gmail.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/types.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/module.h>
+#include <sys/rman.h>
+#include <vm/vm.h>
+#include <vm/vm_kern.h>
+#include <vm/pmap.h>
+#include <vm/vm_page.h>
+#include <vm/vm_extern.h>
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <machine/resource.h>
+
+#include "econa_reg.h"
+#include "econa_var.h"
+
+static struct econa_softc *econa_softc;
+
+unsigned int CPU_clock = 200000000;
+unsigned int AHB_clock;
+unsigned int APB_clock;
+
+bs_protos(generic);
+bs_protos(generic_armv4);
+
+struct bus_space econa_bs_tag = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ generic_bs_map,
+ generic_bs_unmap,
+ generic_bs_subregion,
+
+ /* allocation/deallocation */
+ generic_bs_alloc,
+ generic_bs_free,
+
+ /* barrier */
+ generic_bs_barrier,
+
+ /* read (single) */
+ generic_bs_r_1,
+ generic_armv4_bs_r_2,
+ generic_bs_r_4,
+ NULL,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ generic_armv4_bs_rm_2,
+ generic_bs_rm_4,
+ NULL,
+
+ /* read region */
+ generic_bs_rr_1,
+ generic_armv4_bs_rr_2,
+ generic_bs_rr_4,
+ NULL,
+
+ /* write (single) */
+ generic_bs_w_1,
+ generic_armv4_bs_w_2,
+ generic_bs_w_4,
+ NULL,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ generic_armv4_bs_wm_2,
+ generic_bs_wm_4,
+ NULL,
+
+ /* write region */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set multiple */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* set region */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* copy */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* read (single) stream */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* read multiple stream */
+ NULL,
+ generic_armv4_bs_rm_2,
+ NULL,
+ NULL,
+
+ /* read region stream */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* write (single) stream */
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+
+ /* write multiple stream */
+ NULL,
+ generic_armv4_bs_wm_2,
+ NULL,
+ NULL,
+
+ /* write region stream */
+ NULL,
+ NULL,
+ NULL,
+ NULL
+};
+
+bus_space_tag_t obio_tag = &econa_bs_tag;
+
+static int
+econa_probe(device_t dev)
+{
+
+ device_set_desc(dev, "ECONA device bus");
+ return (0);
+}
+
+static void
+econa_identify(driver_t *drv, device_t parent)
+{
+
+ BUS_ADD_CHILD(parent, 0, "econaarm", 0);
+}
+
+struct arm32_dma_range *
+bus_dma_get_range(void)
+{
+
+ return (NULL);
+}
+
+int
+bus_dma_get_range_nb(void)
+{
+
+ return (0);
+}
+
+extern void irq_entry(void);
+
+static void
+econa_add_child(device_t dev, int prio, const char *name, int unit,
+ bus_addr_t addr, bus_size_t size,
+ int irq0, int irq1,
+ int irq2, int irq3, int irq4)
+{
+ device_t kid;
+ struct econa_ivar *ivar;
+
+ kid = device_add_child_ordered(dev, prio, name, unit);
+ if (kid == NULL) {
+ printf("Can't add child %s%d ordered\n", name, unit);
+ return;
+ }
+ ivar = malloc(sizeof(*ivar), M_DEVBUF, M_NOWAIT | M_ZERO);
+ if (ivar == NULL) {
+ device_delete_child(dev, kid);
+ return;
+ }
+ device_set_ivars(kid, ivar);
+ resource_list_init(&ivar->resources);
+ if (irq0 != -1)
+ bus_set_resource(kid, SYS_RES_IRQ, 0, irq0, 1);
+ if (irq1 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 1, irq1, 1);
+ if (irq2 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 2, irq2, 1);
+ if (irq3 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 3, irq3, 1);
+ if (irq4 != 0)
+ bus_set_resource(kid, SYS_RES_IRQ, 4, irq4, 1);
+
+ if (addr != 0)
+ bus_set_resource(kid, SYS_RES_MEMORY, 0, addr, size);
+
+}
+
+struct cpu_devs
+{
+ const char *name;
+ int unit;
+ bus_addr_t mem_base;
+ bus_size_t mem_len;
+ int irq0;
+ int irq1;
+ int irq2;
+ int irq3;
+ int irq4;
+};
+
+struct cpu_devs econarm_devs[] =
+{
+ {
+ "econa_ic", 0,
+ ECONA_IO_BASE + ECONA_PIC_BASE, ECONA_PIC_SIZE,
+ 0
+ },
+ {
+ "system", 0,
+ ECONA_IO_BASE + ECONA_SYSTEM_BASE, ECONA_SYSTEM_SIZE,
+ 0
+ },
+ {
+ "uart", 0,
+ ECONA_IO_BASE + ECONA_UART_BASE, ECONA_UART_SIZE,
+ ECONA_IRQ_UART
+ },
+ {
+ "timer", 0,
+ ECONA_IO_BASE + ECONA_TIMER_BASE, ECONA_TIMER_SIZE,
+ ECONA_IRQ_TIMER_1, ECONA_IRQ_TIMER_2
+ },
+ {
+ "ohci", 0,
+ ECONA_OHCI_VBASE, ECONA_OHCI_SIZE,
+ ECONA_IRQ_OHCI
+ },
+ {
+ "ehci", 0,
+ ECONA_EHCI_VBASE, ECONA_EHCI_SIZE,
+ ECONA_IRQ_EHCI
+ },
+ {
+ "cfi", 0,
+ ECONA_CFI_VBASE, ECONA_CFI_SIZE,
+ 0
+ },
+ {
+ "ece", 0,
+ ECONA_IO_BASE + ECONA_NET_BASE, ECONA_NET_SIZE,
+ ECONA_IRQ_STATUS,
+ ECONA_IRQ_TSTC, ECONA_IRQ_FSRC,
+ ECONA_IRQ_TSQE, ECONA_IRQ_FSQF,
+ },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+};
+
+static void
+econa_cpu_add_builtin_children(device_t dev, struct econa_softc *sc)
+{
+ int i;
+ struct cpu_devs *walker;
+
+ for (i = 0, walker = econarm_devs; walker->name; i++, walker++) {
+ econa_add_child(dev, i, walker->name, walker->unit,
+ walker->mem_base, walker->mem_len,
+ walker->irq0,walker->irq1, walker->irq2,
+ walker->irq3, walker->irq4);
+ }
+
+}
+
+struct intc_trigger_t {
+ int mode;
+ int level;
+};
+
+static struct intc_trigger_t intc_trigger_table[] = {
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_EDGE_TRIGGER, INTC_FALLING_EDGE},
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_EDGE_TRIGGER, INTC_FALLING_EDGE},
+ {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
+ {INTC_TRIGGER_UNKNOWN, INTC_TRIGGER_UNKNOWN},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_HIGH},
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_EDGE_TRIGGER, INTC_RISING_EDGE},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
+ {INTC_LEVEL_TRIGGER, INTC_ACTIVE_LOW},
+};
+
+static inline uint32_t
+read_4(struct econa_softc *sc, bus_size_t off)
+{
+
+ return bus_space_read_4(sc->ec_st, sc->ec_sys_sh, off);
+}
+
+static inline void
+write_4(struct econa_softc *sc, bus_size_t off, uint32_t val)
+{
+
+ return bus_space_write_4(sc->ec_st, sc->ec_sys_sh, off, val);
+}
+
+static inline uint32_t
+system_read_4(struct econa_softc *sc, bus_size_t off)
+{
+
+ return bus_space_read_4(sc->ec_st, sc->ec_system_sh, off);
+}
+
+static inline void
+system_write_4(struct econa_softc *sc, bus_size_t off, uint32_t val)
+{
+
+ return bus_space_write_4(sc->ec_st, sc->ec_system_sh, off, val);
+}
+
+
+
+static inline void
+econa_set_irq_mode(struct econa_softc * sc, unsigned int irq,
+ unsigned int mode)
+{
+ unsigned int val;
+
+ if ((mode != INTC_LEVEL_TRIGGER) && (mode != INTC_EDGE_TRIGGER))
+ return;
+
+ val = read_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET);
+
+ if (mode == INTC_LEVEL_TRIGGER) {
+ if (val & (1UL << irq)) {
+ val &= ~(1UL << irq);
+ write_4(sc, INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET,
+ val);
+ }
+ } else {
+ if (!(val & (1UL << irq))) {
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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