svn commit: r190704 - head/sys/powerpc/aim

Rafal Jaworowski raj at
Sun Apr 5 02:04:00 PDT 2009

On 2009-04-05, at 00:23, Marcel Moolenaar wrote:

> Author: marcel
> Date: Sat Apr  4 22:23:03 2009
> New Revision: 190704
> URL:
> Log:
>  Perform a dummy stwcx. when we switch contexts. The context
>  being switched out may hold a reservation. The stwcx. will
>  clear the reservation. This is architecturally recommended.
>  The scenario this addresses is as follows:
>  1. Thread 1 performs a lwarx and as such holds a reservation.
>  2. Thread 1 gets switched out (before doing the matching
>     stwcx.) and thread 2 is switched in.
>  3. Thread 2 performs a stwcx. to the same reservation granule.
>     This will succeed because the processor has the reservation
>     even though thread 2 didn't do the lwarx.
>  Note that on some processors the address given the stwcx. is
>  not checked. On these processors the mere condition of having
>  a reservation would cause the stwcx. to succeed, irrespective
>  of whether the addresses are the same. The dummy stwcx. is
>  especially important for those processors.

Have you seen this false stwcx. actually succeed in some real  
scenarios on AIM? Were there any tangible [corruption?] effects  
observed without this fix?

We're seeing some hang with the dual E500 under very heavy loads, but  
only with ULE (or we could only correlate this with ULE so far), but  
didn't get to really close investigation of this issue yet. I'm  
wondering if it's something of this sort too.


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