svn commit: r184916 - head/lib/libpmc
Joseph Koshy
jkoshy at FreeBSD.org
Thu Nov 13 02:21:56 PST 2008
Author: jkoshy
Date: Thu Nov 13 10:21:56 2008
New Revision: 184916
URL: http://svn.freebsd.org/changeset/base/184916
Log:
Fix typos, document UMASK values.
Modified:
head/lib/libpmc/pmc.core2.3
Modified: head/lib/libpmc/pmc.core2.3
==============================================================================
--- head/lib/libpmc/pmc.core2.3 Thu Nov 13 10:14:30 2008 (r184915)
+++ head/lib/libpmc/pmc.core2.3 Thu Nov 13 10:21:56 2008 (r184916)
@@ -226,48 +226,48 @@ The default is to measure both snoops.
Core2 programmable PMCs support the following events:
.Bl -tag -width indent
.It Li BACLEARS
-.Pq Event E6H
+.Pq Event E6H , Umask 00H
The number of times the front end is resteered.
.It Li BOGUS_BR
-.Pq Event E4H
+.Pq Event E4H , Umask 00H
The number of byte sequences mistakenly detected as taken branch
instructions.
.It Li BR_BAC_MISSP_EXEC
-.Pq Event 8AH
+.Pq Event 8AH , Umask 00H
The number of branch instructions that were mispredicted when
decoded.
.It Li BR_CALL_MISSP_EXEC
-.Pq Event 93H
+.Pq Event 93H , Umask 00H
The number of mispredicted
.Li CALL
instructions that were executed.
.It Li BR_CALL_EXEC
-.Pq Event 92H
+.Pq Event 92H , Umask 00H
The number of
.Li CALL
instructions executed.
.It Li BR_CND_EXEC
-.Pq Event 8BH
+.Pq Event 8BH , Umask 00H
The number of conditional branches executed, but not necessarily retired.
.It Li BR_CND_MISSP_EXEC
-.Pq Event 8CH
+.Pq Event 8CH , Umask 00H
The number of mispredicted conditional branches executed.
.It Li BR_IND_CALL_EXEC
-.Pq Event 94H
+.Pq Event 94H , Umask 00H
The number of indirect
.Li CALL
instructions executed.
.It Li BR_IND_EXEC
-.Pq Event 8DH
+.Pq Event 8DH , Umask 00H
The number of indirect branch instructions executed.
.It Li BR_IND_MISSP_EXEC
-.Pq Event 8EH
+.Pq Event 8EH , Umask 00H
The number of mispredicted indirect branch instructions executed.
.It Li BR_INST_DECODED
-.Pq Event E0H
+.Pq Event E0H , Umask 00H
The number of branch instructions decoded.
.It Li BR_INST_EXEC
-.Pq Event 88H
+.Pq Event 88H , Umask 00H
The number of branches executed, but not necessarily retired.
.It Li BR_INST_RETIRED.ANY
.Pq Event C4H , Umask 00H
@@ -298,28 +298,28 @@ predicted.
.Pq Event C4H , Umask 0CH
The number of taken branch instructions retired.
.It Li BR_MISSP_EXEC
-.Pq Event 89H
+.Pq Event 89H , Umask 00H
The number of mispredicted branch instructions that were executed.
.It Li BR_RET_MISSP_EXEC
-.Pq Event 90H
+.Pq Event 90H , Umask 00H
The number of mispredicted
.Li RET
instructions executed.
.It Li BR_RET_BAC_MISSP_EXEC
-.Pq Event 91H
+.Pq Event 91H , Umask 00H
The number of
.Li RET
instructions executed that were mispredicted at decode time.
.It Li BR_RET_EXEC
-.Pq Event 8FH
+.Pq Event 8FH , Umask 00H
The number of
.Li RET
instructions executed.
.It Li BR_TKN_BUBBLE_1
-.Pq Event 97H
+.Pq Event 97H , Umask 00H
The number of branch predicted taken with bubble 1.
.It Li BR_TKN_BUBBLE_2
-.Pq Event 98H
+.Pq Event 98H , Umask 00H
The number of branch predicted taken with bubble 2.
.It Li BUSQ_EMPTY Op ,core= Ns Ar core
.Pq Event 7DH
@@ -463,7 +463,7 @@ This is an architectural performance eve
The number of bus cycles during which the core remains unhalted and
the other core is halted.
.It Li CYCLES_DIV_BUSY
-.Pq Event 14H
+.Pq Event 14H , Umask 00H
The number of cycles the divider is busy.
This event is only available on PMC0.
.It Li CYCLES_INT_MASKED
@@ -474,7 +474,7 @@ The number of cycles during which interr
The number of cycles during which there were pending interrupts while
interrupts were disabled.
.It Li CYCLES_L1I_MEM_STALLED
-.Pq Event 86H
+.Pq Event 86H , Umask 00H
The number of cycles for which an instruction fetch stalls.
.It Li DELAYED_BYPASS.FP
.Pq Event 19H , Umask 00H
@@ -488,7 +488,7 @@ The number of delayed bypass penalty cyc
The number of times SIMD operations use data immediately after data,
was generated by a non-SIMD execution unit.
.It Li DIV
-.Pq Event 13H
+.Pq Event 13H , Umask 00H
The number of divide operations executed.
This event is only available on PMC1.
.It Li DTLB_MISSES.ANY
@@ -505,7 +505,7 @@ The number of Data TLB misses due to loa
.Pq Event 08H , Umask 08H
The number of Data TLB misses due to store operations.
.It Li EIST_TRANS
-.Pq Event 3AH
+.Pq Event 3AH , Umask 00H
The number of Enhanced Intel SpeedStep Technology transitions.
.It Li ESP.ADDITIONS
.Pq Event ABH , Umask 02H
@@ -529,11 +529,11 @@ instruction.
.Pq Event 77H
The number of snoop responses to bus transactions.
.It Li FP_ASSIST
-.Pq Event 11H
+.Pq Event 11H , Umask 00H
The number of floating point operations executed that needed
a microcode assist.
.It Li FP_COMP_OPS_EXE
-.Pq Event 10H
+.Pq Event 10H , Umask 00H
The number of floating point computational micro-ops executed.
The event is available only on PMC0.
.It Li FP_MMX_TRANS_TO_FP
@@ -545,19 +545,19 @@ instructions.
The number of transitions from floating point instructions to MMX
instructions.
.It Li HW_INT_RCV
-.Pq Event C8H
+.Pq Event C8H , Umask 00H
The number of hardware interrupts recieved.
.It Li IDLE_DURING_DIV
-.Pq Event 18H
+.Pq Event 18H , Umask 00H
The number of cycles the divider is busy and no other execution unit
or load operation was in progress.
This event is available only on PMC0.
.It Li ILD_STALL
-.Pq Event 87H
+.Pq Event 87H , Umask 00H
The number of cycles the instruction length decoder stalled due to a
length changing prefix.
.It Li INST_QUEUE.FULL
-.Pq Event 83H
+.Pq Event 83H , Umask 02H
The number of cycles during which the instruction queue is full.
.It Li INST_RETIRED.ANY_P
.Pq Event C0H , Umask 00H
@@ -568,14 +568,15 @@ This is an architectural performance eve
.Pq Event C0H , Umask 01H
The number of instructions retired that contained a load operation.
.It Li INST_RETIRED.OTHER
-.Pq Event C0H
+.Pq Event C0H , Umask 04H
The number of instructions retired that did not contain a load or a
store operation.
.It Li INST_RETIRED.STORES
-.Pq Event C0H
+.Pq Event C0H , Umask 02H
The number of instructions retired that contained a store operation.
.It Li INST_RETIRED.VM_H
-.Pq Event C0H , Tn Core2Extreme
+.Pq Event C0H , Umask 08H
+.Pq Tn Core2Extreme
The number of instructions retired while in VMX root operation.
.It Li ITLB.FLUSH
.Pq Event 82H , Umask 40H
@@ -592,7 +593,7 @@ miss the ITLB.
.Pq Event 82H , Umask 02H
The number of instruction fetches from small pages that miss the ITLB.
.It Li ITLB_MISS_RETIRED
-.Pq Event C9H
+.Pq Event C9H , Umask 00H
The number of retired instructions that missed the ITLB when they were
fetched.
.It Li L1D_ALL_REF
@@ -606,7 +607,7 @@ The number of data reads and writes to c
.Pq Event 42H
The number of locked reads from cacheable memory.
.It Li L1D_CACHE_LOCK_DURATION
-.Pq Event 42H
+.Pq Event 42H , Umask 10H
The number of cycles during which any cache line is locked by any
locking instruction.
.It Li L1D_CACHE_LD Op ,cachestate= Ns Ar state
@@ -618,20 +619,20 @@ reads.
The number of data writes to cacheable memory excluding locked
writes.
.It Li L1D_M_EVICT
-.Pq Event 47H
+.Pq Event 47H , Umask 00H
The number of modified cache lines evicted from L1 data cache.
.It Li L1D_M_REPL
-.Pq Event 46H
+.Pq Event 46H , Umask 00H
The number of modified lines allocated in L1 data cache.
.It Li L1D_PEND_MISS
-.Pq Event 48H
+.Pq Event 48H , Umask 00H
The total number of outstanding L1 data cache misses at any clock.
-.It Li L1D_PREFETCH.
-.Pq Event 4EH
+.It Li L1D_PREFETCH.REQUESTS
+.Pq Event 4EH , Umask 10H
The number of times L1 data cache requested to prefetch a data cache
line.
.It Li L1D_REPL
-.Pq Event 45H
+.Pq Event 45H , Umask 0FH
The number of lines brought into L1 data cache.
.It Li L1D_SPLIT.LOADS
.Pq Event 49H , Umask 01H
@@ -640,10 +641,10 @@ The number of load operations that span
.Pq Event 49H , Umask 02H
The number of store operations that span two cache lines.
.It Li L1I_MISSES
-.Pq Event 81H
+.Pq Event 81H , Umask 00H
The number of instruction fetch unit misses.
.It Li L1I_READS
-.Pq Event 80H
+.Pq Event 80H , Umask 00H
The number of instruction fetches.
.It Li L2_ADS Op ,core= Ns core
.Pq Event 21H
@@ -750,7 +751,7 @@ whose data value is not known.
.Pq Event 03H , Umask 10H
The numer of load operations that were blocked until retirement.
.It Li LOAD_HIT_PRE
-.Pq Event 4CH
+.Pq Event 4CH , Umask 00H
The number of load operations that conflicted with an prefetch to the
same cache line.
.It Li MACHINE_NUKES.SMC
@@ -793,7 +794,7 @@ bus request.
.Pq Event CBH , Umask 04H
The number of load operations that missed L2 cache.
.It Li MUL
-.Pq Event 12H
+.Pq Event 12H , Umask 00H
The number of multiply operations executed.
This event is only available on PMC1.
.It Li PAGE_WALKS.COUNT
@@ -804,11 +805,11 @@ The number of page walks executed due to
The number of cycles spent in a page walk caused by an ITLB or DTLB
miss.
.It Li PREF_RQSTS_DN
-.Pq Event F8H
+.Pq Event F8H , Umask 00H
The number of downward prefetches issued from the Data Prefetch Logic
unit to L2 cache.
.It Li PREF_RQSTS_UP
-.Pq Event F0H
+.Pq Event F0H , Umask 00H
The number of upward prefetches issued from the Data Prefetch Logic
unit to L2 cache.
.It Li RAT_STALLS.ANY
@@ -882,14 +883,14 @@ The number of cycles micro-ops were disp
The number of cycles micro-ops were dispatched for execution on port
4.
.It Li RS_UOPS_DISPATCHED.PORT5
-.Pq Event A1H , Umask 20
+.Pq Event A1H , Umask 20H
The number of cycles micro-ops were dispatched for execution on port
5.
.It Li SB_DRAIN_CYCLES
.Pq Event 04H , Umask 01H
The number of cycles while the store buffer is draining.
.It Li SEGMENT_REG_LOADS
-.Pq Event 06H
+.Pq Event 06H , Umask 00H
The number of segment register loads.
.It Li SEG_REG_RENAMES.ANY
.Pq Event D5H , Umask 0FH
@@ -939,7 +940,7 @@ The number of stalls due to lack of rena
.Li %gs
register.
.It Li SIMD_ASSIST
-.Pq Event CDH
+.Pq Event CDH , Umask 00H
The number SIMD assists invoked.
.It Li SIMD_COMP_INST_RETIRED.PACKED_DOUBLE
.Pq Event CAH , Umask 04H
@@ -958,7 +959,7 @@ retired.
Then number of computational SSE2 scalar single precision instructions
retired.
.It Li SIMD_INSTR_RETIRED
-.Pq Event CEH
+.Pq Event CEH , Umask 00H
The number of retired SIMD instructions that use MMX registers.
.It Li SIMD_INST_RETIRED.ANY
.Pq Event C7H , Umask 1FH
@@ -979,13 +980,13 @@ The number of SSE scalar single precisio
.Pq Event C7H , Umask 10H
The number of SSE2 vector instructions retired.
.It Li SIMD_SAT_INSTR_RETIRED
-.Pq Event CFH
+.Pq Event CFH , Umask 00H
The number of saturated arithmetic SIMD instructions retired.
.It Li SIMD_SAT_UOP_EXEC
-.Pq Event B1H
+.Pq Event B1H , Umask 00H
The number of SIMD saturated arithmetic micro-ops executed.
.It Li SIMD_UOPS_EXEC
-.Pq Event B0H
+.Pq Event B0H , Umask 00H
The number of SIMD micro-ops executed.
.It Li SIMD_UOP_TYPE_EXEC.ARITHMETIC
.Pq Event B3H , Umask 20H
@@ -1053,7 +1054,7 @@ globally observed.
The number of cycles while a store was blocked due to a conflict with
an internal or external snoop.
.It Li THERMAL_TRIP
-.Pq Event 3BH
+.Pq Event 3BH , Umask C0H
The number of thermal trips.
.It Li UOPS_RETIRED.LD_IND_BR
.Pq Event C2H , Umask 01H
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