svn commit: r294416 - in head/sys: arm/conf arm/mv arm/mv/armada38x boot/fdt/dts/arm conf
Zbigniew Bodek
zbb at FreeBSD.org
Wed Jan 20 13:14:38 UTC 2016
Author: zbb
Date: Wed Jan 20 13:14:36 2016
New Revision: 294416
URL: https://svnweb.freebsd.org/changeset/base/294416
Log:
Introduce initial support for Marvell Armada38x
This commit introduces initial support for Marvell Armada38x platform.
Changes:
- Add common DTS files for Armada38x SoCs and DTS file for A388-GP
- Add ARMADA38X kernel configuration
- Add option SOC_MV_ARMADA38X and set MV_PCI_PORTS
- Add list of files to compile
- Implement get_tclk(), get_sar_value(), cpu_reset() functions
- Add CPU ID and SoC numbers
- Correct ifdefs in arm/mv/timer.c
Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst at semihalf.com>
Differential revision: https://reviews.freebsd.org/D4210
Added:
head/sys/arm/conf/ARMADA38X (contents, props changed)
head/sys/arm/mv/armada38x/
head/sys/arm/mv/armada38x/armada38x.c (contents, props changed)
head/sys/arm/mv/armada38x/files.armada38x (contents, props changed)
head/sys/arm/mv/armada38x/std.armada38x (contents, props changed)
head/sys/boot/fdt/dts/arm/armada-380.dtsi (contents, props changed)
head/sys/boot/fdt/dts/arm/armada-385.dtsi (contents, props changed)
head/sys/boot/fdt/dts/arm/armada-388-gp.dts (contents, props changed)
head/sys/boot/fdt/dts/arm/armada-388.dtsi (contents, props changed)
head/sys/boot/fdt/dts/arm/armada-38x.dtsi (contents, props changed)
Modified:
head/sys/arm/mv/mv_common.c
head/sys/arm/mv/mvreg.h
head/sys/arm/mv/mvvar.h
head/sys/arm/mv/mvwin.h
head/sys/arm/mv/timer.c
head/sys/conf/options.arm
Added: head/sys/arm/conf/ARMADA38X
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/conf/ARMADA38X Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,63 @@
+#
+# Kernel configuration for Marvell Armada38x
+#
+# $FreeBSD$
+#
+
+include "../mv/armada38x/std.armada38x"
+include "std.armv6"
+
+ident ARMADA38X
+
+options SOC_MV_ARMADA38X
+
+makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
+makeoptions WERROR="-Werror"
+
+options MD_ROOT
+#makeoptions MFS_IMAGE=/path/to/miniroot
+options ROOTDEVNAME=\"ufs:md0\"
+
+options SCHED_ULE # ULE scheduler
+#options SCHED_4BSD # 4BSD scheduler
+
+# Debugging
+#options DEBUG
+#options VERBOSE_SYSINIT
+options ALT_BREAK_TO_DEBUGGER
+options DDB
+#options GDB
+#options DIAGNOSTIC
+options INVARIANTS # Enable calls of extra sanity checking
+options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS
+options KDB
+options KDB_TRACE
+#options WITNESS # Enable checks to detect deadlocks and cycles
+#options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed
+#options WITNESS_KDB
+#options BOOTVERBOSE
+
+# Pseudo devices
+device random
+device pty
+device loop
+device md
+
+# Serial ports
+device uart
+device uart_ns8250
+
+# Network
+device ether
+device vlan
+
+# Interrupt controllers
+device gic
+
+# Timers
+device mpcore_timer
+
+#FDT
+options FDT
+options FDT_DTB_STATIC
+makeoptions FDT_DTS_FILE=armada-388-gp.dts
Added: head/sys/arm/mv/armada38x/armada38x.c
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/mv/armada38x/armada38x.c Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,54 @@
+/*-
+ * Copyright (c) 2015 Semihalf.
+ * Copyright (c) 2015 Stormshield.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+
+#include <arm/mv/mvwin.h>
+#include <arm/mv/mvreg.h>
+#include <arm/mv/mvvar.h>
+
+uint32_t
+get_tclk(void)
+{
+ uint32_t sar;
+
+ /*
+ * On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
+ * Current setting is read from Sample At Reset register.
+ */
+ sar = (uint32_t)get_sar_value();
+ sar = (sar & TCLK_MASK) >> TCLK_SHIFT;
+ if (sar == 0)
+ return (TCLK_250MHZ);
+ else
+ return (TCLK_200MHZ);
+}
Added: head/sys/arm/mv/armada38x/files.armada38x
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/mv/armada38x/files.armada38x Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,4 @@
+# $FreeBSD$
+
+arm/mv/armada38x/armada38x.c standard
+arm/mv/rtc.c standard
Added: head/sys/arm/mv/armada38x/std.armada38x
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/arm/mv/armada38x/std.armada38x Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,10 @@
+# $FreeBSD$
+files "../mv/armada38x/files.armada38x"
+files "../mv/files.mv"
+cpu CPU_CORTEXA
+machine arm armv6
+
+makeoptions CONF_CFLAGS="-march=armv7a"
+makeoptions KERNVIRTADDR=0xc0000000
+
+options KERNVIRTADDR=0xc0000000
Modified: head/sys/arm/mv/mv_common.c
==============================================================================
--- head/sys/arm/mv/mv_common.c Wed Jan 20 12:19:34 2016 (r294415)
+++ head/sys/arm/mv/mv_common.c Wed Jan 20 13:14:36 2016 (r294416)
@@ -260,7 +260,7 @@ write_cpu_ctrl(uint32_t reg, uint32_t va
bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
}
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
uint32_t
read_cpu_mp_clocks(uint32_t reg)
{
@@ -294,7 +294,7 @@ void
cpu_reset(void)
{
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X)
write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
#else
@@ -442,6 +442,15 @@ soc_identify(void)
else if (r == 1)
rev = "A1";
break;
+ case MV_DEV_88F6828:
+ dev = "Marvell 88F6828";
+ break;
+ case MV_DEV_88F6820:
+ dev = "Marvell 88F6820";
+ break;
+ case MV_DEV_88F6810:
+ dev = "Marvell 88F6810";
+ break;
case MV_DEV_MV78100_Z0:
dev = "Marvell MV78100 Z0";
break;
@@ -2195,6 +2204,10 @@ get_sar_value(void)
SAMPLE_AT_RESET_HI);
sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
SAMPLE_AT_RESET_LO);
+#elif defined(SOC_MV_ARMADA38X)
+ sar_high = 0;
+ sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
+ SAMPLE_AT_RESET);
#else
/*
* TODO: Add getting proper values for other SoC configurations
Modified: head/sys/arm/mv/mvreg.h
==============================================================================
--- head/sys/arm/mv/mvreg.h Wed Jan 20 12:19:34 2016 (r294415)
+++ head/sys/arm/mv/mvreg.h Wed Jan 20 13:14:36 2016 (r294416)
@@ -123,7 +123,7 @@
/*
* System reset
*/
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define RSTOUTn_MASK 0x60
#define SYSTEM_SOFT_RESET 0x64
#define WD_RSTOUTn_MASK 0x4
@@ -346,6 +346,8 @@
#define SAMPLE_AT_RESET 0x30
#elif defined(SOC_MV_FREY)
#define SAMPLE_AT_RESET 0x100
+#elif defined(SOC_MV_ARMADA38X)
+#define SAMPLE_AT_RESET 0x400
#endif
#if defined(SOC_MV_DISCOVERY)
#define SAMPLE_AT_RESET_LO 0x30
@@ -370,6 +372,9 @@
#elif defined(SOC_MV_LOKIPLUS)
#define TCLK_MASK 0x0000F000
#define TCLK_SHIFT 0x0C
+#elif defined(SOC_MV_ARMADA38X)
+#define TCLK_MASK 0x00008000
+#define TCLK_SHIFT 15
#endif
#define TCLK_100MHZ 100000000
@@ -415,6 +420,9 @@
#define MV_DEV_88F6281 0x6281
#define MV_DEV_88F6282 0x6282
#define MV_DEV_88F6781 0x6781
+#define MV_DEV_88F6828 0x6828
+#define MV_DEV_88F6820 0x6820
+#define MV_DEV_88F6810 0x6810
#define MV_DEV_MV78100_Z0 0x6381
#define MV_DEV_MV78100 0x7810
#define MV_DEV_MV78130 0x7813
Modified: head/sys/arm/mv/mvvar.h
==============================================================================
--- head/sys/arm/mv/mvvar.h Wed Jan 20 12:19:34 2016 (r294415)
+++ head/sys/arm/mv/mvvar.h Wed Jan 20 13:14:36 2016 (r294416)
@@ -109,7 +109,7 @@ uint32_t get_l2clk(void);
uint32_t read_cpu_ctrl(uint32_t);
void write_cpu_ctrl(uint32_t, uint32_t);
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
uint32_t read_cpu_mp_clocks(uint32_t reg);
void write_cpu_mp_clocks(uint32_t reg, uint32_t val);
uint32_t read_cpu_misc(uint32_t reg);
Modified: head/sys/arm/mv/mvwin.h
==============================================================================
--- head/sys/arm/mv/mvwin.h Wed Jan 20 12:19:34 2016 (r294415)
+++ head/sys/arm/mv/mvwin.h Wed Jan 20 13:14:36 2016 (r294416)
@@ -73,6 +73,8 @@
#define MV_PCI_PORTS 2 /* 2x PCIE */
#elif defined(SOC_MV_ARMADAXP)
#define MV_PCI_PORTS 3 /* 3x PCIE */
+#elif defined(SOC_MV_ARMADA38X)
+#define MV_PCI_PORTS 4 /* 4x PCIE */
#else
#error "MV_PCI_PORTS not configured !"
#endif
@@ -129,7 +131,7 @@
#endif
#define MV_MPP_BASE (MV_BASE + 0x10000)
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_MISC_BASE (MV_BASE + 0x18200)
#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000)
#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80)
Modified: head/sys/arm/mv/timer.c
==============================================================================
--- head/sys/arm/mv/timer.c Wed Jan 20 12:19:34 2016 (r294415)
+++ head/sys/arm/mv/timer.c Wed Jan 20 13:14:36 2016 (r294416)
@@ -54,7 +54,7 @@ __FBSDID("$FreeBSD$");
#define INITIAL_TIMECOUNTER (0xffffffff)
#define MAX_WATCHDOG_TICKS (0xffffffff)
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
#define MV_CLOCK_SRC 25000000 /* Timers' 25MHz mode */
#else
#define MV_CLOCK_SRC get_tclk()
@@ -124,7 +124,7 @@ mv_timer_attach(device_t dev)
int error;
void *ihl;
struct mv_timer_softc *sc;
-#if !defined(SOC_MV_ARMADAXP)
+#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_cause, irq_mask;
#endif
@@ -155,7 +155,7 @@ mv_timer_attach(device_t dev)
}
mv_setup_timers();
-#if !defined(SOC_MV_ARMADAXP)
+#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
irq_cause &= IRQ_TIMER0_CLR;
@@ -294,7 +294,7 @@ static void
mv_watchdog_enable(void)
{
uint32_t val, irq_cause;
-#if !defined(SOC_MV_ARMADAXP)
+#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_mask;
#endif
@@ -302,7 +302,7 @@ mv_watchdog_enable(void)
irq_cause &= IRQ_TIMER_WD_CLR;
write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
@@ -318,7 +318,7 @@ mv_watchdog_enable(void)
val = mv_get_timer_control();
val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO;
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val |= CPU_TIMER_WD_25MHZ_EN;
#endif
mv_set_timer_control(val);
@@ -328,7 +328,7 @@ static void
mv_watchdog_disable(void)
{
uint32_t val, irq_cause;
-#if !defined(SOC_MV_ARMADAXP)
+#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
uint32_t irq_mask;
#endif
@@ -336,7 +336,7 @@ mv_watchdog_disable(void)
val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
mv_set_timer_control(val);
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
@@ -438,7 +438,7 @@ mv_setup_timers(void)
val = mv_get_timer_control();
val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO);
val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO;
-#if defined(SOC_MV_ARMADAXP)
+#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X)
/* Enable 25MHz mode */
val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN;
#endif
Added: head/sys/boot/fdt/dts/arm/armada-380.dtsi
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/armada-380.dtsi Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,154 @@
+/*
+ * Device Tree Include file for Marvell Armada 380 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior at marvell.com>
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+#include "armada-38x.dtsi"
+
+/ {
+ model = "Marvell Armada 380 family SoC";
+ compatible = "marvell,armada380";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,armada-380-smp";
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ pinctrl at 18000 {
+ compatible = "marvell,mv88f6810-pinctrl";
+ };
+ };
+
+ pcie-controller {
+ compatible = "marvell,armada-370-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+ 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
+
+ /* x1 port */
+ pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ /* x1 port */
+ pcie at 2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ /* x1 port */
+ pcie at 3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+ };
+ };
+};
Added: head/sys/boot/fdt/dts/arm/armada-385.dtsi
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/armada-385.dtsi Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,186 @@
+/*
+ * Device Tree Include file for Marvell Armada 385 SoC.
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Lior Amsalem <alior at marvell.com>
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+#include "armada-38x.dtsi"
+
+/ {
+ model = "Marvell Armada 385 family SoC";
+ compatible = "marvell,armada385", "marvell,armada380";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "marvell,armada-380-smp";
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ internal-regs {
+ pinctrl at 18000 {
+ compatible = "marvell,mv88f6820-pinctrl";
+ };
+ };
+
+ pcie-controller {
+ compatible = "marvell,armada-370-pcie";
+ status = "disabled";
+ device_type = "pci";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ msi-parent = <&mpic>;
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+ 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+ 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+ 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
+ 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+ 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
+ 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+ 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
+ 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+ 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
+
+ /*
+ * This port can be either x4 or x1. When
+ * configured in x4 by the bootloader, then
+ * pcie at 4,0 is not available.
+ */
+ pcie at 1,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+ reg = <0x0800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+ 0x81000000 0 0 0x81000000 0x1 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <0>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 8>;
+ status = "disabled";
+ };
+
+ /* x1 port */
+ pcie at 2,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+ reg = <0x1000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <1>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 5>;
+ status = "disabled";
+ };
+
+ /* x1 port */
+ pcie at 3,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+ reg = <0x1800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+ 0x81000000 0 0 0x81000000 0x3 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <2>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 6>;
+ status = "disabled";
+ };
+
+ /*
+ * x1 port only available when pcie at 1,0 is
+ * configured as a x1 port
+ */
+ pcie at 4,0 {
+ device_type = "pci";
+ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+ reg = <0x2000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+ 0x81000000 0 0 0x81000000 0x4 0 1 0>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ marvell,pcie-port = <3>;
+ marvell,pcie-lane = <0>;
+ clocks = <&gateclk 7>;
+ status = "disabled";
+ };
+ };
+ };
+};
Added: head/sys/boot/fdt/dts/arm/armada-388-gp.dts
==============================================================================
--- /dev/null 00:00:00 1970 (empty, because file is newly added)
+++ head/sys/boot/fdt/dts/arm/armada-388-gp.dts Wed Jan 20 13:14:36 2016 (r294416)
@@ -0,0 +1,415 @@
+/*
+ * Device Tree file for Marvell Armada 385 development board
+ * (RD-88F6820-GP)
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement at free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without
+ * any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+#include "armada-388.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Marvell Armada 385 GP";
+ compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000>; /* 2 GB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+ internal-regs {
+ spi at 10600 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+
+ spi-flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ };
+ };
+
+ i2c at 11000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+ /*
+ * The EEPROM located at adresse 54 is needed
+ * for the boot - DO NOT ERASE IT -
+ */
+
+ expander0: pca9555 at 20 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pca0_pins>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20>;
+ };
+
+ expander1: pca9555 at 21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio0>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x21>;
+ };
+
+ };
+
+ serial at 12000 {
+ /*
+ * Exported on the micro USB connector CON16
+ * through an FTDI
+ */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+ };
+
+ /* GE1 CON15 */
+ ethernet at 30000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ };
+
+ /* CON4 */
+ usb at 58000 {
+ vcc-supply = <®_usb2_0_vbus>;
+ status = "okay";
+ };
+
+ /* GE0 CON1 */
+ ethernet at 70000 {
+ pinctrl-names = "default";
+ /*
+ * The Reference Clock 0 is used to provide a
+ * clock to the PHY
+ */
+ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ };
+
+
+ mdio at 72004 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ phy0: ethernet-phy at 1 {
+ reg = <1>;
+ };
+
+ phy1: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ };
+
+ sata at a8000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port at 0 {
+ reg = <0>;
+ target-supply = <®_5v_sata0>;
+ };
+
+ sata1: sata-port at 1 {
+ reg = <1>;
+ target-supply = <®_5v_sata1>;
+ };
+ };
+
+ sata at e0000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata2: sata-port at 0 {
+ reg = <0>;
+ target-supply = <®_5v_sata2>;
+ };
+
+ sata3: sata-port at 1 {
+ reg = <1>;
+ target-supply = <®_5v_sata3>;
+ };
+ };
+
+ sdhci at d8000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ wp-inverted;
+ bus-width = <8>;
+ status = "okay";
+ };
+
+ /* CON5 */
+ usb3 at f0000 {
+ vcc-supply = <®_usb2_1_vbus>;
+ status = "okay";
+ };
+
+ /* CON7 */
+ usb3 at f8000 {
+ vcc-supply = <®_usb3_vbus>;
+ status = "okay";
+ };
+ };
+
+ pcie-controller {
+ status = "okay";
+ /*
+ * One PCIe units is accessible through
+ * standard PCIe slot on the board.
+ */
+ pcie at 1,0 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+ };
+
+ /*
+ * The two other PCIe units are accessible
+ * through mini PCIe slot on the board.
+ */
+ pcie at 2,0 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+ };
+ pcie at 3,0 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+ };
+ };
+
+ gpio-fan {
+ compatible = "gpio-fan";
+ gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
+ gpio-fan,speed-map = < 0 0
+ 3000 1>;
+ };
+ };
+
+ reg_usb3_vbus: usb3-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_usb2_0_vbus: v5-vbus0 {
+ compatible = "regulator-fixed";
+ regulator-name = "v5.0-vbus0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_usb2_1_vbus: v5-vbus1 {
+ compatible = "regulator-fixed";
+ regulator-name = "v5.0-vbus1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_usb2_1_vbus: v5-vbus1 {
+ compatible = "regulator-fixed";
+ regulator-name = "v5.0-vbus1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_sata0: pwr-sata0 {
+ compatible = "regulator-fixed";
+ regulator-name = "pwr_en_sata0";
+ enable-active-high;
+ regulator-always-on;
*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
More information about the svn-src-all
mailing list